📄 rccu.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.40A/W32 17/Jan/2007 16:16:26 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = arm /
// Endian = little /
// Stack alignment = 4 /
// Source file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu. /
// c /
// Command line = "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu. /
// c" -lC "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\D /
// ebug\List\" -lA "D:\lilian\STR71X\application /
// note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2 /
// .0\user\Debug\List\" -o "D:\lilian\STR71X\applicati /
// on note\IAP using UART\an2078_IAR(forum)\an2078\IAP /
// _V2.0\user\Debug\Obj\" -z2 --no_cse --no_unroll /
// --no_inline --no_code_motion --no_tbaa /
// --no_clustering --no_scheduling --debug --cpu_mode /
// arm --endian little --cpu ARM7TDMI --stack_align 4 /
// -e --fpu None --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl4tpannl8n.h" -I /
// "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\..\incl /
// ude\" -I "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\. /
// .\common\" -I ROJ_DIR$\ -I "C:\Program Files\IAR /
// Systems\Embedded Workbench 4.0\arm\INC\" /
// List file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\L /
// ist\rccu.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME rccu
RTMODEL "StackAlign4", "USED"
RTMODEL "__cpu_mode", "__pcs__arm"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "6"
RSEG CSTACK:DATA:NOROOT(2)
EXTERN ??divu32_a
MULTWEAK ??RCCU_Div2Status??rA
MULTWEAK ??rA??divu32_a
PUBWEAK RCCU_Div2Status
FUNCTION RCCU_Div2Status,0203H
PUBLIC RCCU_FrequencyValue
FUNCTION RCCU_FrequencyValue,0203H
LOCFRAME CSTACK, 24, STACK
PUBLIC RCCU_PLL1Config
FUNCTION RCCU_PLL1Config,0203H
LOCFRAME CSTACK, 16, STACK
PUBLIC RCCU_RCLKClockSource
FUNCTION RCCU_RCLKClockSource,0203H
PUBLIC RCCU_RCLKSourceConfig
FUNCTION RCCU_RCLKSourceConfig,0203H
CFI Names cfiNames0
CFI StackFrame CFA R13 HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
CFI Resource R14:32, SPSR:32
CFI VirtualResource ?RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 4
CFI DataAlign 4
CFI ReturnAddress ?RET CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI CPSR SameValue
CFI R14 Undefined
CFI SPSR SameValue
CFI ?RET R14
CFI EndCommon cfiCommon0
RCCU_Div2Status SYMBOL "RCCU_Div2Status"
??RCCU_Div2Status??rA SYMBOL "??rA", RCCU_Div2Status
// D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu.c
// 1 /******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
// 2 * File Name : rccu.c
// 3 * Author : MCD Application Team
// 4 * Date First Issued : 07/28/2003
// 5 * Description : This file provides all the RCCU software functions.
// 6 ********************************************************************************
// 7 * History:
// 8 * 02/01/2006 : IAP Version 2.0
// 9 * 11/24/2004 : IAP Version 1.0
// 10 *******************************************************************************
// 11 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
// 12 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
// 13 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
// 14 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
// 15 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
// 16 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
// 17 *******************************************************************************/
// 18 #include "rccu.h"
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock0 Using cfiCommon0
CFI Function RCCU_Div2Status
ARM
// __??Code32?? __code __arm __atpcs FlagStatus RCCU_Div2Status(void)
RCCU_Div2Status:
MOV R0,#-1610612728
LDR R0,[R0, #+0]
TST R0,#0x8000
BEQ ??RCCU_Div2Status_0
MOV R0,#+1
B ??RCCU_Div2Status_1
??RCCU_Div2Status_0:
MOV R0,#+0
??RCCU_Div2Status_1:
MOV PC,LR ;; return
CFI EndBlock cfiBlock0
// 19
// 20 /*******************************************************************************
// 21 * Function Name : RCCU_PLL1Config
// 22 * Description : Configures the PLL1 div & mul factors.
// 23 * Input 1 : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
// 24 * RCCU_PLL1_Mul_24 )
// 25 * Input 2 : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
// 26 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
// 27 * Return : None
// 28 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock1 Using cfiCommon0
CFI Function RCCU_PLL1Config
ARM
// 29 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )
// 30 {
RCCU_PLL1Config:
PUSH {R4-R6,LR}
CFI ?RET Frame(CFA, -4)
CFI R6 Frame(CFA, -8)
CFI R5 Frame(CFA, -12)
CFI R4 Frame(CFA, -16)
CFI CFA R13+16
MOVS R4,R0
MOVS R5,R1
// 31 u32 Tmp = 0;
MOV R0,#+0
MOVS R6,R0
// 32
// 33 if (RCCU_FrequencyValue(RCCU_CLK2)>3000000)
MOV R0,#+0
BL RCCU_FrequencyValue
LDR R1,??RCCU_PLL1Config_0 ;; 0x2dc6c1
CMP R0,R1
BCC ??RCCU_PLL1Config_1
// 34 RCCU->PLL1CR|=RCCU_FREEN_Mask;
MOV R0,#+24
ORR R0,R0,#0xA0000000
MOV R1,#+24
ORR R1,R1,#0xA0000000
LDR R1,[R1, #+0]
ORRS R1,R1,#0x80
STR R1,[R0, #+0]
B ??RCCU_PLL1Config_2
// 35 else
// 36 RCCU->PLL1CR&=~RCCU_FREEN_Mask;
??RCCU_PLL1Config_1:
MOV R0,#+24
ORR R0,R0,#0xA0000000
MOV R1,#+24
ORR R1,R1,#0xA0000000
LDR R1,[R1, #+0]
BICS R1,R1,#0x80
STR R1,[R0, #+0]
// 37
// 38 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
??RCCU_PLL1Config_2:
MOV R0,#+24
ORR R0,R0,#0xA0000000
LDR R0,[R0, #+0]
BICS R0,R0,#0x30
MOVS R1,R4
ORRS R0,R0,R1, LSL #+4
MOVS R6,R0
// 39 RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;
MOV R0,#+24
ORR R0,R0,#0xA0000000
LSRS R1,R6,#+3
MOVS R2,R5
ORRS R1,R2,R1, LSL #+3
ORRS R1,R1,#0x40
STR R1,[R0, #+0]
// 40 }
POP {R4-R6,PC} ;; return
DATA
??RCCU_PLL1Config_0:
DC32 0x2dc6c1
CFI EndBlock cfiBlock1
// 41
// 42 /*******************************************************************************
// 43 * Function Name : RCCU_RCLKSourceConfig
// 44 * Description : Selects the RCLK source clock
// 45 * Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2,
// 46 * RCCU_RTC_CLOCK)
// 47 * Return : None
// 48 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock2 Using cfiCommon0
CFI Function RCCU_RCLKSourceConfig
ARM
// 49 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )
// 50 {
// 51 switch ( New_Clock )
RCCU_RCLKSourceConfig:
MOVS R1,R0
CMP R1,#+3
BHI ??RCCU_RCLKSourceConfig_1
ADR R2,??RCCU_RCLKSourceConfig_0
LDRB R2,[R2, R1]
ADD PC,PC,R2, LSL #+2
DATA
??RCCU_RCLKSourceConfig_0:
DC8 +43,+24,+0,+69
ARM
// 52 {
// 53 case RCCU_CLOCK2 :{ /* Resets the CSU_Cksel bit in clk_flag */
// 54 RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;
??RCCU_RCLKSourceConfig_2:
MOV R1,#-1610612728
MOV R2,#-1610612728
LDR R2,[R2, #+0]
BICS R2,R2,#0x1
STR R2,[R1, #+0]
// 55 /* Set the CK2_16 Bit in the CFR */
// 56 RCCU->CFR |= RCCU_CK2_16_Mask;
MOV R1,#-1610612728
MOV R2,#-1610612728
LDR R2,[R2, #+0]
ORRS R2,R2,#0x8
STR R2,[R1, #+0]
// 57 /* Deselect The CKAF */
// 58 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
MOV R1,#-1610612736
MOV R2,#-1610612736
LDR R2,[R2, #+0]
BICS R2,R2,#0x4
STR R2,[R1, #+0]
// 59 /* switch off the PLL1 */
// 60 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
// 61 |0x00000003) & ~RCCU_FREEN_Mask;
MOV R1,#+24
ORR R1,R1,#0xA0000000
MOV R2,#+24
ORR R2,R2,#0xA0000000
LDR R2,[R2, #+0]
BICS R2,R2,#0x87
ORRS R2,R2,#0x3
STR R2,[R1, #+0]
// 62 break;}
B ??RCCU_RCLKSourceConfig_1
// 63 case RCCU_CLOCK2_16 :{ /* ReSet the CK2_16 Bit in the CFR */
// 64 RCCU->CFR &= ~RCCU_CK2_16_Mask;
??RCCU_RCLKSourceConfig_3:
MOV R1,#-1610612728
MOV R2,#-1610612728
LDR R2,[R2, #+0]
BICS R2,R2,#0x8
STR R2,[R1, #+0]
// 65 /* Deselect The CKAF */
// 66 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
MOV R1,#-1610612736
MOV R2,#-1610612736
LDR R2,[R2, #+0]
BICS R2,R2,#0x4
STR R2,[R1, #+0]
// 67 /* switch off the PLL1 */
// 68 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
// 69 |0x00000003) & ~RCCU_FREEN_Mask;
MOV R1,#+24
ORR R1,R1,#0xA0000000
MOV R2,#+24
ORR R2,R2,#0xA0000000
LDR R2,[R2, #+0]
BICS R2,R2,#0x87
ORRS R2,R2,#0x3
STR R2,[R1, #+0]
// 70 break;}
B ??RCCU_RCLKSourceConfig_1
// 71 case RCCU_PLL1_Output:{ /* Set the CK2_16 Bit in the CFR */
// 72 RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;
??RCCU_RCLKSourceConfig_4:
MOV R1,#-1610612728
MOV R2,#-1610612728
LDR R2,[R2, #+0]
ORRS R2,R2,#0x8
STR R2,[R1, #+0]
// 73 /* Waits the PLL1 to lock if DX bits are different from '111' */
// 74 /* If all DX bit are set the PLL lock flag in meaningless */
// 75 if (( RCCU->PLL1CR & 0x0007 ) != 7)
MOV R1,#+24
ORR R1,R1,#0xA0000000
LDR R1,[R1, #+0]
ANDS R1,R1,#0x7
CMP R1,#+7
BEQ ??RCCU_RCLKSourceConfig_5
// 76 while(!(RCCU->CFR & RCCU_LOCK_Mask));
??RCCU_RCLKSourceConfig_6:
MOV R1,#-1610612728
LDR R1,[R1, #+0]
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