📄 71x_init.lst
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###############################################################################
# #
# IAR Systems ARM Assembler V4.40A/W32 17/Jan/2007 16:16:23 #
# Copyright 1999-2006 IAR Systems. All rights reserved. #
# #
# Source file = D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\71x_init.s#
# List file = D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\List\71x_init.lst#
# Object file = D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\Obj\71x_init.r79#
# Command line = D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\71x_init.s #
# -OD:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\Obj\ #
# -s+ -M<> -w+ -r #
# -LD:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\List\ #
# -t8 -x --cpu ARM7TDMI --fpu None #
# -IC:\Program Files\IAR Systems\Embedded Workbench 4.0\arm\INC\ #
# #
###############################################################################
1 00000000 ;******************** (C) COPYRIGHT 2006
STMicroelectronics ********************
2 00000000 ;* File Name : 71x_init.s
3 00000000 ;* Author : MCD Application
Team
4 00000000 ;* Date First Issued : 06/23/2004
5 00000000 ;* Description : This is the first code
executed after RESET.
6 00000000 ;* This code initializes
system stacks and test the P1.8
7 00000000 ;* status to jump to the
IAP or to the user code program.
8 00000000 ;***********************************************
********************************
9 00000000 ;* History:
10 00000000 ;* 02/01/2006 : IAP Version 2.0
11 00000000 ;* 11/24/2004 : IAP Version 1.0
12 00000000 ;***********************************************
********************************
13 00000000 ; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE
ONLY AIMS AT PROVIDING CUSTOMERS WITH
14 00000000 ; CODING INFORMATION REGARDING THEIR PRODUCTS IN
ORDER FOR THEM TO SAVE TIME.
15 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE
HELD LIABLE FOR ANY DIRECT, INDIRECT
16 00000000 ; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
CLAIMS ARISING FROM THE CONTENT
17 00000000 ; OF SUCH SOFTWARE AND/OR THE USE MADE BY
CUSTOMERS OF THE CODING INFORMATION
18 00000000 ; CONTAINED HEREIN IN CONNECTION WITH THEIR
PRODUCTS.
19 00000000 ;***********************************************
********************************/
20 00000000
21 00000000
22 00000000 ; --- Standard definitions of mode bits and
interrupt (I & F) flags in PSRs
23 00000000
24 00000010 Mode_USR EQU 0x10
25 00000011 Mode_FIQ EQU 0x11
26 00000012 Mode_IRQ EQU 0x12
27 00000013 Mode_SVC EQU 0x13
28 00000017 Mode_ABT EQU 0x17
29 0000001B Mode_UNDEF EQU 0x1B
30 0000001F Mode_SYS EQU 0x1F ; available on
ARM Arch 4 and later
31 00000000
32 00000080 I_Bit EQU 0x80 ; when I bit is
set, IRQ is disabled
33 00000040 F_Bit EQU 0x40 ; when F bit is
set, FIQ is disabled
34 00000000
35 00000000
36 00000000 ; --- System memory locations
37 00000000
38 20000000 RAM_Base EQU 0x20000000
39 20010000 RAM_Limit EQU 0x20010000
40 60000000 SRAM_Base EQU 0x60000000
41 20010000 Stack_Base EQU RAM_Limit
42 00000000
43 E0004000 GPIO1_Base_addr EQU 0xE0004000; GPIO1
base address
44 00000000 PC0_off_addr EQU 0x00 ; Port
Configuration Register 0 offset
45 00000004 PC1_off_addr EQU 0x04 ; Port
Configuration Register 1 offset
46 00000008 PC2_off_addr EQU 0x08 ; Port
Configuration Register 2 offset
47 0000000C PD_off_addr EQU 0x0C ; Port Data
Register offset
48 00000000
49 00000000 ; add by lilian to access EIC
50 FFFFF800 EIC_BASE EQU 0xFFFFF800
51 00000000
52 00000000 ;|----------------------------------------------
------------------------------------|
53 00000000 ;| ---> User code address
|
54 00000000 ;|----------------------------------------------
------------------------------------|
55 40002000 Flash_Program EQU 0x40002000
56 00000000
57 00000000
58 00000000 ;-----------------------------------------------
----------------
59 00000000 ; ?program_start
60 00000000 ;-----------------------------------------------
----------------
61 00000000 MODULE ?program_start
62 00000000 RSEG IRQ_STACK:DATA(2)
63 00000000 RSEG FIQ_STACK:DATA(2)
64 00000000 RSEG UND_STACK:DATA(2)
65 00000000 RSEG ABT_STACK:DATA(2)
66 00000000 RSEG SVC_STACK:DATA(2)
67 00000000 RSEG CSTACK:DATA(2)
68 00000000 RSEG ICODE:CODE(2)
69 00000000 PUBLIC __program_start
70 00000000 EXTERN ?main
71 00000000 CODE32
72 00000000
73 00000000
74 00000000
75 00000000 ; define remapping
76 00000000 ; If you need to remap memory before entring the
main program
77 00000000 ; uncomment next ligne
78 00000000 #define remapping
79 00000000
80 00000000 ; Then define which memory to remap to address
0x00000000
81 00000000 ; Uncomment next line if you want to remap
RAM
82 00000000 #define remap_ram
83 00000000
84 00000000 ; Uncomment next line if you want to remap
FLASH
85 00000000 ; #define remap_flash
86 00000000
87 00000000 __program_start:
88 00000000 A0F09FE5 LDR pc, =NextInst
89 00000004 NextInst
90 00000004 0000A0E1 NOP ; Wait for OSC
stabilization
91 00000008 0000A0E1 NOP
92 0000000C 0000A0E1 NOP
93 00000010 0000A0E1 NOP
94 00000014 0000A0E1 NOP
95 00000018 0000A0E1 NOP
96 0000001C 0000A0E1 NOP
97 00000020 0000A0E1 NOP
98 00000024 0000A0E1 NOP
99 00000028
100 00000028 D7F021E3 MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
101 0000002C 78D09FE5 LDR SP, =SFE(ABT_STACK )& 0xFFFFFFF8
102 00000030
103 00000030 DBF021E3 MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
104 00000034 74D09FE5 LDR SP,= SFE(UND_STACK) & 0xFFFFFFF8
105 00000038
106 00000038 D3F021E3 MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
107 0000003C 70D09FE5 LDR SP, =SFE(SVC_STACK) & 0xFFFFFFF8
108 00000040
109 00000040 ; here add extra code for close interrupt :
EIC->ICR=0 add by lilian
110 00000040 70009FE5 LDR R0,=EIC_BASE
111 00000044 0010A0E3 LDR R1,=0x0
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