📄 rccu.lst
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\ 0000004C 002092E5 LDR R2,[R2, #+0]
\ 00000050 0420D2E3 BICS R2,R2,#0x4
\ 00000054 002081E5 STR R2,[R1, #+0]
59 /* switch off the PLL1 */
60 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
61 |0x00000003) & ~RCCU_FREEN_Mask;
\ 00000058 1810A0E3 MOV R1,#+24
\ 0000005C A01481E3 ORR R1,R1,#0xA0000000
\ 00000060 1820A0E3 MOV R2,#+24
\ 00000064 A02482E3 ORR R2,R2,#0xA0000000
\ 00000068 002092E5 LDR R2,[R2, #+0]
\ 0000006C 8720D2E3 BICS R2,R2,#0x87
\ 00000070 032092E3 ORRS R2,R2,#0x3
\ 00000074 002081E5 STR R2,[R1, #+0]
62 break;}
\ 00000078 310000EA B ??RCCU_RCLKSourceConfig_1
63 case RCCU_CLOCK2_16 :{ /* ReSet the CK2_16 Bit in the CFR */
64 RCCU->CFR &= ~RCCU_CK2_16_Mask;
\ ??RCCU_RCLKSourceConfig_3:
\ 0000007C 8A12A0E3 MOV R1,#-1610612728
\ 00000080 8A22A0E3 MOV R2,#-1610612728
\ 00000084 002092E5 LDR R2,[R2, #+0]
\ 00000088 0820D2E3 BICS R2,R2,#0x8
\ 0000008C 002081E5 STR R2,[R1, #+0]
65 /* Deselect The CKAF */
66 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ 00000090 A014A0E3 MOV R1,#-1610612736
\ 00000094 A024A0E3 MOV R2,#-1610612736
\ 00000098 002092E5 LDR R2,[R2, #+0]
\ 0000009C 0420D2E3 BICS R2,R2,#0x4
\ 000000A0 002081E5 STR R2,[R1, #+0]
67 /* switch off the PLL1 */
68 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
69 |0x00000003) & ~RCCU_FREEN_Mask;
\ 000000A4 1810A0E3 MOV R1,#+24
\ 000000A8 A01481E3 ORR R1,R1,#0xA0000000
\ 000000AC 1820A0E3 MOV R2,#+24
\ 000000B0 A02482E3 ORR R2,R2,#0xA0000000
\ 000000B4 002092E5 LDR R2,[R2, #+0]
\ 000000B8 8720D2E3 BICS R2,R2,#0x87
\ 000000BC 032092E3 ORRS R2,R2,#0x3
\ 000000C0 002081E5 STR R2,[R1, #+0]
70 break;}
\ 000000C4 1E0000EA B ??RCCU_RCLKSourceConfig_1
71 case RCCU_PLL1_Output:{ /* Set the CK2_16 Bit in the CFR */
72 RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;
\ ??RCCU_RCLKSourceConfig_4:
\ 000000C8 8A12A0E3 MOV R1,#-1610612728
\ 000000CC 8A22A0E3 MOV R2,#-1610612728
\ 000000D0 002092E5 LDR R2,[R2, #+0]
\ 000000D4 082092E3 ORRS R2,R2,#0x8
\ 000000D8 002081E5 STR R2,[R1, #+0]
73 /* Waits the PLL1 to lock if DX bits are different from '111' */
74 /* If all DX bit are set the PLL lock flag in meaningless */
75 if (( RCCU->PLL1CR & 0x0007 ) != 7)
\ 000000DC 1810A0E3 MOV R1,#+24
\ 000000E0 A01481E3 ORR R1,R1,#0xA0000000
\ 000000E4 001091E5 LDR R1,[R1, #+0]
\ 000000E8 071011E2 ANDS R1,R1,#0x7
\ 000000EC 070051E3 CMP R1,#+7
\ 000000F0 0300000A BEQ ??RCCU_RCLKSourceConfig_5
76 while(!(RCCU->CFR & RCCU_LOCK_Mask));
\ ??RCCU_RCLKSourceConfig_6:
\ 000000F4 8A12A0E3 MOV R1,#-1610612728
\ 000000F8 001091E5 LDR R1,[R1, #+0]
\ 000000FC 020011E3 TST R1,#0x2
\ 00000100 FBFFFF0A BEQ ??RCCU_RCLKSourceConfig_6
77 /* Deselect The CKAF */
78 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ ??RCCU_RCLKSourceConfig_5:
\ 00000104 A014A0E3 MOV R1,#-1610612736
\ 00000108 A024A0E3 MOV R2,#-1610612736
\ 0000010C 002092E5 LDR R2,[R2, #+0]
\ 00000110 0420D2E3 BICS R2,R2,#0x4
\ 00000114 002081E5 STR R2,[R1, #+0]
79 /* Select The CSU_CKSEL */
80 RCCU->CFR |= RCCU_CSU_CKSEL_Mask;
\ 00000118 8A12A0E3 MOV R1,#-1610612728
\ 0000011C 8A22A0E3 MOV R2,#-1610612728
\ 00000120 002092E5 LDR R2,[R2, #+0]
\ 00000124 012092E3 ORRS R2,R2,#0x1
\ 00000128 002081E5 STR R2,[R1, #+0]
81 break;}
\ 0000012C 040000EA B ??RCCU_RCLKSourceConfig_1
82 case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04;
\ ??RCCU_RCLKSourceConfig_7:
\ 00000130 A014A0E3 MOV R1,#-1610612736
\ 00000134 A024A0E3 MOV R2,#-1610612736
\ 00000138 002092E5 LDR R2,[R2, #+0]
\ 0000013C 042092E3 ORRS R2,R2,#0x4
\ 00000140 002081E5 STR R2,[R1, #+0]
83 break;}
84 }
85 }
\ ??RCCU_RCLKSourceConfig_1:
\ 00000144 0EF0A0E1 MOV PC,LR ;; return
86
87 /*******************************************************************************
88 * Function Name : RCCU_RCLKClockSource
89 * Description : Returns the current RCLK source clock
90 * Input : None
91 * Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK
92 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
93 RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )
94 {
95 if ((RCCU->CCR & 0x04)==0x04)
\ RCCU_RCLKClockSource:
\ 00000000 A004A0E3 MOV R0,#-1610612736
\ 00000004 000090E5 LDR R0,[R0, #+0]
\ 00000008 040010E3 TST R0,#0x4
\ 0000000C 0100000A BEQ ??RCCU_RCLKClockSource_0
96 return RCCU_RTC_CLOCK;
\ 00000010 0300A0E3 MOV R0,#+3
\ 00000014 0C0000EA B ??RCCU_RCLKClockSource_1
97
98 else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)
\ ??RCCU_RCLKClockSource_0:
\ 00000018 8A02A0E3 MOV R0,#-1610612728
\ 0000001C 000090E5 LDR R0,[R0, #+0]
\ 00000020 080010E3 TST R0,#0x8
\ 00000024 0100001A BNE ??RCCU_RCLKClockSource_2
99 return RCCU_CLOCK2_16;
\ 00000028 0100A0E3 MOV R0,#+1
\ 0000002C 060000EA B ??RCCU_RCLKClockSource_1
100
101 else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)
\ ??RCCU_RCLKClockSource_2:
\ 00000030 8A02A0E3 MOV R0,#-1610612728
\ 00000034 000090E5 LDR R0,[R0, #+0]
\ 00000038 010010E3 TST R0,#0x1
\ 0000003C 0100000A BEQ ??RCCU_RCLKClockSource_3
102 return RCCU_PLL1_Output;
\ 00000040 0000A0E3 MOV R0,#+0
\ 00000044 000000EA B ??RCCU_RCLKClockSource_1
103
104 else
105 return RCCU_CLOCK2;
\ ??RCCU_RCLKClockSource_3:
\ 00000048 0200A0E3 MOV R0,#+2
\ ??RCCU_RCLKClockSource_1:
\ 0000004C 0EF0A0E1 MOV PC,LR ;; return
106 }
107
108 /*******************************************************************************
109 * Function Name : RCCU_FrequencyValue
110 * Description : Calculates & Returns any internal RCCU clock frequency
111 * passed in parametres
112 * Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )
113 * Return : u32
114 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
115 u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )
116 {
\ RCCU_FrequencyValue:
\ 00000000 F0412DE9 PUSH {R4-R8,LR}
\ 00000004 0040B0E1 MOVS R4,R0
117 u32 Tmp;
118 u8 Div = 0;
\ 00000008 0000A0E3 MOV R0,#+0
\ 0000000C 0050B0E1 MOVS R5,R0
119 u8 Mul = 0;
\ 00000010 0000A0E3 MOV R0,#+0
\ 00000014 0060B0E1 MOVS R6,R0
120 RCCU_RCLK_Clocks CurrentRCLK;
121
122 Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc;
\ 00000018 ........ _BLF RCCU_Div2Status,??RCCU_Div2Status??rA
\ 0000001C 010050E3 CMP R0,#+1
\ 00000020 0200001A BNE ??RCCU_FrequencyValue_3
\ 00000024 7A88A0E3 MOV R8,#+7995392
\ 00000028 488D88E3 ORR R8,R8,#0x1200
\ 0000002C 010000EA B ??RCCU_FrequencyValue_4
\ ??RCCU_FrequencyValue_3:
\ 00000030 F488A0E3 MOV R8,#+15990784
\ 00000034 908D88E3 ORR R8,R8,#0x2400
123
124 if ( Internal_Clk == RCCU_CLK2 )
\ ??RCCU_FrequencyValue_4:
\ 00000038 000054E3 CMP R4,#+0
\ 0000003C 0400001A BNE ??RCCU_FrequencyValue_5
125 {
126 Div = 1;
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