📄 rccu.lst
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# #
# IAR ARM ANSI C/C++ Compiler V4.40A/W32 17/Jan/2007 16:16:26 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = arm #
# Endian = little #
# Stack alignment = 4 #
# Source file = D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu.c #
# Command line = "D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu.c #
# " -lC "D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\Li #
# st\" -lA "D:\lilian\STR71X\application note\IAP #
# using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\De #
# bug\List\" -o "D:\lilian\STR71X\application #
# note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2. #
# 0\user\Debug\Obj\" -z2 --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --cpu_mode #
# arm --endian little --cpu ARM7TDMI --stack_align 4 #
# -e --fpu None --dlib_config "C:\Program Files\IAR #
# Systems\Embedded Workbench #
# 4.0\arm\LIB\dl4tpannl8n.h" -I #
# "D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\..\inclu #
# de\" -I "D:\lilian\STR71X\application note\IAP #
# using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\.. #
# \common\" -I ROJ_DIR$\ -I "C:\Program Files\IAR #
# Systems\Embedded Workbench 4.0\arm\INC\" #
# List file = D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\Li #
# st\rccu.lst #
# Object file = D:\lilian\STR71X\application note\IAP using #
# UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\Ob #
# j\rccu.r79 #
# #
# #
##############################################################################
D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\rccu.c
1 /******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
2 * File Name : rccu.c
3 * Author : MCD Application Team
4 * Date First Issued : 07/28/2003
5 * Description : This file provides all the RCCU software functions.
6 ********************************************************************************
7 * History:
8 * 02/01/2006 : IAP Version 2.0
9 * 11/24/2004 : IAP Version 1.0
10 *******************************************************************************
11 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
12 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
13 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
14 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
15 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
16 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *******************************************************************************/
18 #include "rccu.h"
\ In segment CODE, align 4, keep-with-next
\ __??Code32?? __code __arm __atpcs FlagStatus RCCU_Div2Status(void)
\ RCCU_Div2Status:
\ 00000000 8A02A0E3 MOV R0,#-1610612728
\ 00000004 000090E5 LDR R0,[R0, #+0]
\ 00000008 800C10E3 TST R0,#0x8000
\ 0000000C 0100000A BEQ ??RCCU_Div2Status_0
\ 00000010 0100A0E3 MOV R0,#+1
\ 00000014 000000EA B ??RCCU_Div2Status_1
\ ??RCCU_Div2Status_0:
\ 00000018 0000A0E3 MOV R0,#+0
\ ??RCCU_Div2Status_1:
\ 0000001C 0EF0A0E1 MOV PC,LR ;; return
19
20 /*******************************************************************************
21 * Function Name : RCCU_PLL1Config
22 * Description : Configures the PLL1 div & mul factors.
23 * Input 1 : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
24 * RCCU_PLL1_Mul_24 )
25 * Input 2 : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
26 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
27 * Return : None
28 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
29 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )
30 {
\ RCCU_PLL1Config:
\ 00000000 70402DE9 PUSH {R4-R6,LR}
\ 00000004 0040B0E1 MOVS R4,R0
\ 00000008 0150B0E1 MOVS R5,R1
31 u32 Tmp = 0;
\ 0000000C 0000A0E3 MOV R0,#+0
\ 00000010 0060B0E1 MOVS R6,R0
32
33 if (RCCU_FrequencyValue(RCCU_CLK2)>3000000)
\ 00000014 0000A0E3 MOV R0,#+0
\ 00000018 ........ BL RCCU_FrequencyValue
\ 0000001C 7C109FE5 LDR R1,??RCCU_PLL1Config_0 ;; 0x2dc6c1
\ 00000020 010050E1 CMP R0,R1
\ 00000024 0700003A BCC ??RCCU_PLL1Config_1
34 RCCU->PLL1CR|=RCCU_FREEN_Mask;
\ 00000028 1800A0E3 MOV R0,#+24
\ 0000002C A00480E3 ORR R0,R0,#0xA0000000
\ 00000030 1810A0E3 MOV R1,#+24
\ 00000034 A01481E3 ORR R1,R1,#0xA0000000
\ 00000038 001091E5 LDR R1,[R1, #+0]
\ 0000003C 801091E3 ORRS R1,R1,#0x80
\ 00000040 001080E5 STR R1,[R0, #+0]
\ 00000044 060000EA B ??RCCU_PLL1Config_2
35 else
36 RCCU->PLL1CR&=~RCCU_FREEN_Mask;
\ ??RCCU_PLL1Config_1:
\ 00000048 1800A0E3 MOV R0,#+24
\ 0000004C A00480E3 ORR R0,R0,#0xA0000000
\ 00000050 1810A0E3 MOV R1,#+24
\ 00000054 A01481E3 ORR R1,R1,#0xA0000000
\ 00000058 001091E5 LDR R1,[R1, #+0]
\ 0000005C 8010D1E3 BICS R1,R1,#0x80
\ 00000060 001080E5 STR R1,[R0, #+0]
37
38 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
\ ??RCCU_PLL1Config_2:
\ 00000064 1800A0E3 MOV R0,#+24
\ 00000068 A00480E3 ORR R0,R0,#0xA0000000
\ 0000006C 000090E5 LDR R0,[R0, #+0]
\ 00000070 3000D0E3 BICS R0,R0,#0x30
\ 00000074 0410B0E1 MOVS R1,R4
\ 00000078 010290E1 ORRS R0,R0,R1, LSL #+4
\ 0000007C 0060B0E1 MOVS R6,R0
39 RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;
\ 00000080 1800A0E3 MOV R0,#+24
\ 00000084 A00480E3 ORR R0,R0,#0xA0000000
\ 00000088 A611B0E1 LSRS R1,R6,#+3
\ 0000008C 0520B0E1 MOVS R2,R5
\ 00000090 811192E1 ORRS R1,R2,R1, LSL #+3
\ 00000094 401091E3 ORRS R1,R1,#0x40
\ 00000098 001080E5 STR R1,[R0, #+0]
40 }
\ 0000009C 7080BDE8 POP {R4-R6,PC} ;; return
\ ??RCCU_PLL1Config_0:
\ 000000A0 C1C62D00 DC32 0x2dc6c1
41
42 /*******************************************************************************
43 * Function Name : RCCU_RCLKSourceConfig
44 * Description : Selects the RCLK source clock
45 * Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2,
46 * RCCU_RTC_CLOCK)
47 * Return : None
48 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
49 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )
50 {
51 switch ( New_Clock )
\ RCCU_RCLKSourceConfig:
\ 00000000 0010B0E1 MOVS R1,R0
\ 00000004 030051E3 CMP R1,#+3
\ 00000008 4D00008A BHI ??RCCU_RCLKSourceConfig_1
\ 0000000C 012F8FE2 ADR R2,??RCCU_RCLKSourceConfig_0
\ 00000010 0120D2E7 LDRB R2,[R2, R1]
\ 00000014 02F18FE0 ADD PC,PC,R2, LSL #+2
\ ??RCCU_RCLKSourceConfig_0:
\ 00000018 2B180045 DC8 +43,+24,+0,+69
52 {
53 case RCCU_CLOCK2 :{ /* Resets the CSU_Cksel bit in clk_flag */
54 RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;
\ ??RCCU_RCLKSourceConfig_2:
\ 0000001C 8A12A0E3 MOV R1,#-1610612728
\ 00000020 8A22A0E3 MOV R2,#-1610612728
\ 00000024 002092E5 LDR R2,[R2, #+0]
\ 00000028 0120D2E3 BICS R2,R2,#0x1
\ 0000002C 002081E5 STR R2,[R1, #+0]
55 /* Set the CK2_16 Bit in the CFR */
56 RCCU->CFR |= RCCU_CK2_16_Mask;
\ 00000030 8A12A0E3 MOV R1,#-1610612728
\ 00000034 8A22A0E3 MOV R2,#-1610612728
\ 00000038 002092E5 LDR R2,[R2, #+0]
\ 0000003C 082092E3 ORRS R2,R2,#0x8
\ 00000040 002081E5 STR R2,[R1, #+0]
57 /* Deselect The CKAF */
58 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ 00000044 A014A0E3 MOV R1,#-1610612736
\ 00000048 A024A0E3 MOV R2,#-1610612736
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