📄 gpio.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.40A/W32 17/Jan/2007 16:16:24 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = arm /
// Endian = little /
// Stack alignment = 4 /
// Source file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\gpio. /
// c /
// Command line = "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\gpio. /
// c" -lC "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\D /
// ebug\List\" -lA "D:\lilian\STR71X\application /
// note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2 /
// .0\user\Debug\List\" -o "D:\lilian\STR71X\applicati /
// on note\IAP using UART\an2078_IAR(forum)\an2078\IAP /
// _V2.0\user\Debug\Obj\" -z2 --no_cse --no_unroll /
// --no_inline --no_code_motion --no_tbaa /
// --no_clustering --no_scheduling --debug --cpu_mode /
// arm --endian little --cpu ARM7TDMI --stack_align 4 /
// -e --fpu None --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl4tpannl8n.h" -I /
// "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\..\incl /
// ude\" -I "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\. /
// .\common\" -I ROJ_DIR$\ -I "C:\Program Files\IAR /
// Systems\Embedded Workbench 4.0\arm\INC\" /
// List file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\L /
// ist\gpio.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME gpio
RTMODEL "StackAlign4", "USED"
RTMODEL "__cpu_mode", "__pcs__arm"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "6"
RSEG CSTACK:DATA:NOROOT(2)
PUBLIC GPIO_Config
FUNCTION GPIO_Config,0203H
CFI Names cfiNames0
CFI StackFrame CFA R13 HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
CFI Resource R14:32, SPSR:32
CFI VirtualResource ?RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 4
CFI DataAlign 4
CFI ReturnAddress ?RET CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI CPSR SameValue
CFI R14 Undefined
CFI SPSR SameValue
CFI ?RET R14
CFI EndCommon cfiCommon0
// D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\source\gpio.c
// 1 /******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
// 2 * File Name : gpio.c
// 3 * Author : MCD Application Team
// 4 * Date First Issued : 06/08/2003
// 5 * Description : This file provides all the GPIO software functions.
// 6 ********************************************************************************
// 7 * History:
// 8 * 02/01/2006 : IAP Version 2.0
// 9 * 11/24/2004 : IAP Version 1.0
// 10 *******************************************************************************
// 11 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
// 12 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
// 13 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
// 14 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
// 15 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
// 16 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
// 17 *******************************************************************************/
// 18
// 19 #include "gpio.h"
// 20
// 21 /*******************************************************************************
// 22 * Function Name : GPIO_Config
// 23 * Description : Configure the GPIO port pins.
// 24 * Input 1 : GPIOx (x can be 0,1 or 2) the desired port.
// 25 * Input 2 : Port_Pins : pins placements.
// 26 * Input 3 : Pins Mode(GPIO_HI_AIN_TRI,GPIO_IN_TRI_TTL,GPIO_IN_TRI_CMOS,
// 27 * GPIO_IPUPD_WP,GPIO_OUT_OD,GPIO_OUT_PP,GPIO_AF_OD,GPIO_AF_PP).
// 28 * Output : None
// 29 * Return : None
// 30 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock0 Using cfiCommon0
CFI Function GPIO_Config
ARM
// 31 void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode)
// 32 {
// 33 switch (GPIO_Mode)
GPIO_Config:
MOVS R3,R2
CMP R3,#+7
BHI ??GPIO_Config_1
ADR R12,??GPIO_Config_0
LDRB R12,[R12, R3]
ADD PC,PC,R12, LSL #+2
DATA
??GPIO_Config_0:
DC8 +1,+11,+21,+31
DC8 +41,+51,+61,+71
ARM
// 34 {
// 35 case GPIO_HI_AIN_TRI:
// 36 GPIOx->PC0&=~Port_Pins;
??GPIO_Config_2:
LDRH R3,[R0, #+0]
BICS R3,R3,R1
STRH R3,[R0, #+0]
// 37 GPIOx->PC1&=~Port_Pins;
LDRH R3,[R0, #+4]
BICS R3,R3,R1
STRH R3,[R0, #+4]
// 38 GPIOx->PC2&=~Port_Pins;
LDRH R3,[R0, #+8]
BICS R3,R3,R1
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 39 break;
// 40
// 41 case GPIO_IN_TRI_TTL:
// 42 GPIOx->PC0|=Port_Pins;
??GPIO_Config_3:
LDRH R3,[R0, #+0]
ORRS R3,R1,R3
STRH R3,[R0, #+0]
// 43 GPIOx->PC1&=~Port_Pins;
LDRH R3,[R0, #+4]
BICS R3,R3,R1
STRH R3,[R0, #+4]
// 44 GPIOx->PC2&=~Port_Pins;
LDRH R3,[R0, #+8]
BICS R3,R3,R1
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 45 break;
// 46
// 47 case GPIO_IN_TRI_CMOS:
// 48 GPIOx->PC0&=~Port_Pins;
??GPIO_Config_4:
LDRH R3,[R0, #+0]
BICS R3,R3,R1
STRH R3,[R0, #+0]
// 49 GPIOx->PC1|=Port_Pins;
LDRH R3,[R0, #+4]
ORRS R3,R1,R3
STRH R3,[R0, #+4]
// 50 GPIOx->PC2&=~Port_Pins;
LDRH R3,[R0, #+8]
BICS R3,R3,R1
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 51 break;
// 52
// 53 case GPIO_IPUPD_WP:
// 54 GPIOx->PC0|=Port_Pins;
??GPIO_Config_5:
LDRH R3,[R0, #+0]
ORRS R3,R1,R3
STRH R3,[R0, #+0]
// 55 GPIOx->PC1|=Port_Pins;
LDRH R3,[R0, #+4]
ORRS R3,R1,R3
STRH R3,[R0, #+4]
// 56 GPIOx->PC2&=~Port_Pins;
LDRH R3,[R0, #+8]
BICS R3,R3,R1
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 57 break;
// 58
// 59 case GPIO_OUT_OD:
// 60 GPIOx->PC0&=~Port_Pins;
??GPIO_Config_6:
LDRH R3,[R0, #+0]
BICS R3,R3,R1
STRH R3,[R0, #+0]
// 61 GPIOx->PC1&=~Port_Pins;
LDRH R3,[R0, #+4]
BICS R3,R3,R1
STRH R3,[R0, #+4]
// 62 GPIOx->PC2|=Port_Pins;
LDRH R3,[R0, #+8]
ORRS R3,R1,R3
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 63 break;
// 64
// 65 case GPIO_OUT_PP:
// 66 GPIOx->PC0|=Port_Pins;
??GPIO_Config_7:
LDRH R3,[R0, #+0]
ORRS R3,R1,R3
STRH R3,[R0, #+0]
// 67 GPIOx->PC1&=~Port_Pins;
LDRH R3,[R0, #+4]
BICS R3,R3,R1
STRH R3,[R0, #+4]
// 68 GPIOx->PC2|=Port_Pins;
LDRH R3,[R0, #+8]
ORRS R3,R1,R3
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 69 break;
// 70
// 71 case GPIO_AF_OD:
// 72 GPIOx->PC0&=~Port_Pins;
??GPIO_Config_8:
LDRH R3,[R0, #+0]
BICS R3,R3,R1
STRH R3,[R0, #+0]
// 73 GPIOx->PC1|=Port_Pins;
LDRH R3,[R0, #+4]
ORRS R3,R1,R3
STRH R3,[R0, #+4]
// 74 GPIOx->PC2|=Port_Pins;
LDRH R3,[R0, #+8]
ORRS R3,R1,R3
STRH R3,[R0, #+8]
B ??GPIO_Config_1
// 75 break;
// 76
// 77 case GPIO_AF_PP:
// 78 GPIOx->PC0|=Port_Pins;
??GPIO_Config_9:
LDRH R3,[R0, #+0]
ORRS R3,R1,R3
STRH R3,[R0, #+0]
// 79 GPIOx->PC1|=Port_Pins;
LDRH R3,[R0, #+4]
ORRS R3,R1,R3
STRH R3,[R0, #+4]
// 80 GPIOx->PC2|=Port_Pins;
LDRH R3,[R0, #+8]
ORRS R3,R1,R3
STRH R3,[R0, #+8]
// 81 break;
// 82 }
// 83 }
??GPIO_Config_1:
MOV PC,LR ;; return
CFI EndBlock cfiBlock0
END
// 84
// 85 /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
//
// 352 bytes in segment CODE
//
// 352 bytes of CODE memory
//
//Errors: none
//Warnings: none
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