📄 api_segment_init.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.40A/W32 28/Nov/2006 11:57:53 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = arm /
// Endian = little /
// Stack alignment = 4 /
// Source file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\api_seg /
// ment_init.c /
// Command line = "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\api_seg /
// ment_init.c" -lC "D:\lilian\STR71X\application /
// note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2 /
// .0\user\Debug\List\" -lA /
// "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\L /
// ist\" -o "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\D /
// ebug\Obj\" -z2 --no_cse --no_unroll --no_inline /
// --no_code_motion --no_tbaa --no_clustering /
// --no_scheduling --debug --cpu_mode arm --endian /
// little --cpu ARM7TDMI --stack_align 4 -e --fpu /
// None --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl4tpannl8n.h" -I /
// "D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\..\incl /
// ude\" -I "D:\lilian\STR71X\application note\IAP /
// using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\. /
// .\common\" -I ROJ_DIR$\ -I "C:\Program Files\IAR /
// Systems\Embedded Workbench 4.0\arm\INC\" /
// List file = D:\lilian\STR71X\application note\IAP using /
// UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\Debug\L /
// ist\api_segment_init.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME api_segment_init
RTMODEL "StackAlign4", "USED"
RTMODEL "__cpu_mode", "__pcs__arm"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "6"
RSEG CSTACK:DATA:NOROOT(2)
RSEG INITTAB:DATA:REORDER:NOROOT(0)
MULTWEAK ??memcpy??rA
MULTWEAK ??memset??rA
PUBLIC init_ram_code
FUNCTION init_ram_code,0201H
LOCFRAME CSTACK, 16, STACK
CFI Names cfiNames0
CFI StackFrame CFA R13 HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, CPSR:32, R13:32
CFI Resource R14:32, SPSR:32
CFI VirtualResource ?RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 4
CFI DataAlign 4
CFI ReturnAddress ?RET CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI CPSR SameValue
CFI R14 Undefined
CFI SPSR SameValue
CFI ?RET R14
CFI EndCommon cfiCommon0
memcpy SYMBOL "memcpy"
memset SYMBOL "memset"
??memcpy??rA SYMBOL "??rA", memcpy
??memset??rA SYMBOL "??rA", memset
EXTERN memcpy
FUNCTION memcpy,010202H
EXTERN memset
FUNCTION memset,010202H
// D:\lilian\STR71X\application note\IAP using UART\an2078_IAR(forum)\an2078\IAP_V2.0\user\api_segment_init.c
// 1 #include <string.h>
// 2 #include "segment_init.h"
// 3
// 4 #pragma language=extended
// 5 #pragma segment="INITTAB"
// 6
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock0 Using cfiCommon0
CFI Function init_ram_code
ARM
// 7 void init_ram_code()
// 8 {
init_ram_code:
PUSH {R4-R6,LR}
CFI ?RET Frame(CFA, -4)
CFI R6 Frame(CFA, -8)
CFI R5 Frame(CFA, -12)
CFI R4 Frame(CFA, -16)
CFI CFA R13+16
// 9 InitBlock_Type const * const initTableBegin = __sfb( "INITTAB" );
LDR R0,??init_ram_code_0 ;; SFB(INITTAB)
MOVS R4,R0
// 10 InitBlock_Type const * const initTableEnd = __sfe( "INITTAB" );
LDR R0,??init_ram_code_0+0x4 ;; SFE(INITTAB)
MOVS R5,R0
// 11 InitBlock_Type const * initTableP;
// 12
// 13 for (initTableP=initTableBegin; (int)initTableP<(int)initTableEnd; initTableP++)
MOVS R6,R4
??init_ram_code_1:
CMP R6,R5
BGE ??init_ram_code_2
// 14 {
// 15 if (initTableP->Src == initTableP->Dst)
LDR R0,[R6, #+8]
LDR R1,[R6, #+4]
CMP R0,R1
BNE ??init_ram_code_3
// 16 {
// 17 memset(initTableP->Dst, 0, initTableP->Size);
LDR R2,[R6, #+0]
MOV R1,#+0
LDR R0,[R6, #+4]
_BLF memset,??memset??rA
B ??init_ram_code_4
// 18 }
// 19 else
// 20 {
// 21 memcpy(initTableP->Dst, initTableP->Src, initTableP->Size);
??init_ram_code_3:
LDR R2,[R6, #+0]
LDR R1,[R6, #+8]
LDR R0,[R6, #+4]
_BLF memcpy,??memcpy??rA
// 22 }
// 23 }
??init_ram_code_4:
ADDS R6,R6,#+12
B ??init_ram_code_1
// 24 }
??init_ram_code_2:
POP {R4-R6,PC} ;; return
DATA
??init_ram_code_0:
DC32 SFB(INITTAB)
DC32 SFE(INITTAB)
CFI EndBlock cfiBlock0
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock1 Using cfiCommon0
CFI NoFunction
ARM
??memset??rA:
LDR R12,??Subroutine0_0 ;; memset
MOV PC,R12
DATA
??Subroutine0_0:
DC32 memset
CFI EndBlock cfiBlock1
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock2 Using cfiCommon0
CFI NoFunction
ARM
??memcpy??rA:
LDR R12,??Subroutine1_0 ;; memcpy
MOV PC,R12
DATA
??Subroutine1_0:
DC32 memcpy
CFI EndBlock cfiBlock2
RSEG INITTAB:DATA:REORDER:NOROOT(0)
END
// 25
// 26 #pragma language=default
//
// 128 bytes in segment CODE
//
// 104 bytes of CODE memory (+ 24 bytes shared)
//
//Errors: none
//Warnings: none
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