📄 cstartup.lst
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###############################################################################
# #
# IAR Systems ARM Assembler V4.31A/W32 27/Nov/2007 14:04:49 #
# Copyright 1999-2006 IAR Systems. All rights reserved. #
# #
# Source file = G:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\SrcIAR\Cstartup.s79#
# List file = G:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\FLASH_Debug\List\Cstartup.lst#
# Object file = G:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\FLASH_Debug\Obj\Cstartup.r79#
# Command line = G:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\SrcIAR\Cstartup.s79 #
# -OG:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\FLASH_Debug\Obj\ #
# -s+ -M<> -w+ -r #
# -LG:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\FLASH_Debug\List\ #
# -t8 --cpu ARM7TDMI --fpu None #
# -IC:\Program Files\IAR Systems\Embedded Workbench 4.0 Evaluation\ARM\INC\ #
# -IG:\AT91_ENERGY\ATMEL_ARM\x256_mmc\AT91SAM7X-Mass Storage\compil\..\..\ #
# #
###############################################################################
1 00000000 ;-----------------------------------------------
-------------------------------
2 00000000 ;- ATMEL Microcontroller Software
Support - ROUSSET -
3 00000000 ;-----------------------------------------------
-------------------------------
4 00000000 ; The software is delivered "AS IS" without
warranty or condition of any
5 00000000 ; kind, either express, implied or statutory.
This includes without
6 00000000 ; limitation any warranty or condition with
respect to merchantability or
7 00000000 ; fitness for any particular purpose, or against
the infringements of
8 00000000 ; intellectual property rights of others.
9 00000000 ;-----------------------------------------------
------------------------------
10 00000000 ;- File source : Cstartup.s79
11 00000000 ;- Object : Generic CStartup for
IAR No Use REMAP
12 00000000 ;- Compilation flag : None
13 00000000 ;-
14 00000000 ;- 1.0 15/Jun/04 JPP : Creation
15 00000000 ;- 1.1 01/Apr/05 JPP : save SPSR
16 00000000 ;-----------------------------------------------
-------------------------------
17 00000000
18 00000000 ;-----------------------------------------------
-------------------------------
19 00000000 ;- Area Definition
20 00000000 ;-----------------------------------------------
-------------------------------
21 00000000
22 FFFFF000 AT91C_BASE_AIC EQU 0xFFFFF000
23 00000104 AIC_FVR EQU (260)
24 00000100 AIC_IVR EQU (256)
25 00000130 AIC_EOICR EQU (304)
26 00000000
27 00000000 ;-----------------------------------------------
----------------
28 00000000 ; ?RESET
29 00000000 ; Reset Vector.
30 00000000 ; Normally, segment INTVEC is linked at address
0.
31 00000000 ; For debugging purposes, INTVEC may be placed
at other
32 00000000 ; addresses.
33 00000000 ; A debugger that honors the entry point will
start the
34 00000000 ; program in a normal way even if INTVEC is not
at address 0.
35 00000000 ;-----------------------------------------------
--------------
36 00000000
37 00000000 PROGRAM ?RESET
38 00000000 RSEG INTRAMSTART_REMAP
39 00000000 RSEG INTRAMEND_REMAP
40 00000000
41 00000000 RSEG ICODE:CODE:ROOT(2)
42 00000000 CODE32 ; Always ARM mode after reset
43 00000000 org 0
44 00000000 reset
45 00000000
46 00000000 ;-----------------------------------------------
-------------------------------
47 00000000 ;- Exception vectors
48 00000000 ;--------------------
49 00000000 ;- These vectors can be read at address 0 or at
RAM address
50 00000000 ;- They ABSOLUTELY requires to be in relative
addresssing mode in order to
51 00000000 ;- guarantee a valid jump. For the moment, all
are just looping.
52 00000000 ;- If an exception occurs before remap, this
would result in an infinite loop.
53 00000000 ;- To ensure if a exeption occurs before start
application to infinite loop.
54 00000000 ;-----------------------------------------------
-------------------------------
55 00000000
56 00000000 0F0000EA B InitReset ; 0x00 Reset
handler
57 00000004 undefvec:
58 00000004 FEFFFFEA B undefvec ; 0x04
Undefined
Instruction
59 00000008 swivec:
60 00000008 FEFFFFEA B swivec ; 0x08
Software
Interrupt
61 0000000C pabtvec:
62 0000000C FEFFFFEA B pabtvec ; 0x0C
Prefetch
Abort
63 00000010 dabtvec:
64 00000010 FEFFFFEA B dabtvec ; 0x10 Data
Abort
65 00000014 rsvdvec:
66 00000014 FEFFFFEA B rsvdvec ; 0x14
reserved
67 00000018 irqvec:
68 00000018 1C0000EA B IRQ_Handler_Entry ; 0x18
IRQ
69 0000001C fiqvec: ; 0x1c
FIQ
70 0000001C ;-----------------------------------------------
-------------------------------
71 0000001C ;- Function : FIQ_Handler_Entry
72 0000001C ;- Treatments : FIQ Controller
Interrupt Handler.
73 0000001C ;- Called Functions : AIC_FVR[interrupt]
74 0000001C ;-----------------------------------------------
-------------------------------
75 0000001C
76 0000001C FIQ_Handler_Entry:
77 0000001C
78 0000001C ;- Switch in SVC/User Mode to allow User Stack
access for C code
79 0000001C ; because the FIQ is not yet acknowledged
80 0000001C
81 0000001C ;- Save and r0 in FIQ_Register
82 0000001C 0090A0E1 mov r9, r0
83 00000020 040198E5 ldr r0, [r8, #AIC_FVR]
84 00000024 D3F021E3 msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_S
VC
85 00000028 ;- Save scratch/used registers and LR in User
Stack
86 00000028 0E502DE9 stmfd sp!, { r1-r3, r12, lr}
87 0000002C
88 0000002C ;- Branch to the routine pointed by the
AIC_FVR
89 0000002C 0FE0A0E1 mov r14, pc
90 00000030 10FF2FE1 bx r0
91 00000034
92 00000034 ;- Restore scratch/used registers and LR from
User Stack
93 00000034 0E50BDE8 ldmia sp!, { r1-r3, r12, lr}
94 00000038
95 00000038 ;- Leave Interrupts disabled and switch back in
FIQ mode
96 00000038 D1F021E3 msr CPSR_c, #I_BIT | F_BIT |
ARM_MODE_FIQ
97 0000003C
98 0000003C ;- Restore the R0 ARM_MODE_SVC register
99 0000003C 0900A0E1 mov r0, r9
100 00000040
101 00000040 ;- Restore the Program Counter using the LR_fiq
directly in the PC
102 00000040 04F05EE2 subs pc, lr, #4
103 00000044
104 00000044
105 00000044 InitReset:
106 00000044 ;-----------------------------------------------
-------------------------------
107 00000044 ;- Low level Init (PMC, AIC, ? ....) by C
function AT91F_LowLevelInit
108 00000044 ;-----------------------------------------------
-------------------------------
109 00000000 EXTERN AT91F_LowLevelInit
110 00000044
111 00000044 #define __iramend SFB(INTRAMEND_REMAP)
112 00000044
113 00000044 ;- minumum C initialization
114 00000044 ;- call AT91F_LowLevelInit( void)
115 00000044
116 00000044 CCD09FE5 ldr r13, =__iramend ;
temporary stack in internal
RAM
117 00000048
118 00000048 ;--Call Low level init function in ABSOLUTE
through the Interworking
119 00000048 CC009FE5 ldr r0, =AT91F_LowLevelInit
120 0000004C 0FE0A0E1 mov lr, pc
121 00000050 10FF2FE1 bx r0
122 00000054
123 00000054 ;-----------------------------------------------
-------------------------------
124 00000054 ;- Stack Sizes Definition
125 00000054 ;------------------------
126 00000054 ;- Interrupt Stack requires 2 words x 8 priority
level x 4 bytes when using
127 00000054 ;- the vectoring. This assume that the IRQ
management.
128 00000054 ;- The Interrupt Stack must be adjusted
depending on the interrupt handlers.
129 00000054 ;- Fast Interrupt not requires stack If in your
application it required you must
130 00000054 ;- be definehere.
131 00000054 ;- The System stack size is not defined and is
limited by the free internal
132 00000054 ;- SRAM.
133 00000054 ;-----------------------------------------------
-------------------------------
134 00000054
135 00000054 ;-----------------------------------------------
-------------------------------
136 00000054 ;- Top of Stack Definition
137 00000054 ;-------------------------
138 00000054 ;- Interrupt and Supervisor Stack are located at
the top of internal memory in
139 00000054 ;- order to speed the exception handling context
saving and restoring.
140 00000054 ;- ARM_MODE_SVC (Application, C) Stack is
located at the top of the external memory.
141 00000054 ;-----------------------------------------------
-------------------------------
142 00000054
143 00000060 IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per
interrupt priority level
144 00000054
145 00000011 ARM_MODE_FIQ EQU 0x11
146 00000012 ARM_MODE_IRQ EQU 0x12
147 00000013 ARM_MODE_SVC EQU 0x13
148 00000054
149 00000080 I_BIT EQU 0x80
150 00000040 F_BIT EQU 0x40
151 00000054
152 00000054 ;-----------------------------------------------
-------------------------------
153 00000054 ;- Setup the stack for each mode
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