📄 fw_task.lst
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\ ??fw_isr_3:
\ 0000009C F007 LSL R0,R6,#+31
\ 0000009E 1CD5 BPL ??fw_isr_4
300 }
301
302
303 /****************************************/
304 /* (UDP) Endpoint 0 Interrupt : EP CTRL */
305 /****************************************/
306 if(_IT_reg_b1 & AT91C_UDP_EPINT0)
307 {
308 fw_ep0RxTxDone();
^
Warning[Ta023]: Call to a non __ramfunc function (fw_ep0RxTxDone) from within
a __ramfunc function
\ 000000A0 ........ _BLF fw_ep0RxTxDone,??fw_ep0RxTxDone??rT?CODE_I
309
310 /* AT91C_UDP_EPINT1 : Endpoint 1 Interrupt */
311 /* AT91C_UDP_EPINT2 : Endpoint 2 Interrupt */
312 AT91F_UDP_EnableIt( USBDEV_BASE_UDP, AT91C_UDP_EPINT1 | AT91C_UDP_EPINT2 );
\ 000000A4 7248 LDR R0,??fw_isr_0+0x24 ;; 0xfffb0010
\ 000000A6 0621 MOV R1,#+6
\ 000000A8 0160 STR R1,[R0, #+0]
313
314 if( AT91F_UDP_EpStatus( USBDEV_BASE_UDP, FW_EP_CTRL ) & USBDEV_UDP_TXCOMP )
\ 000000AA 3868 LDR R0,[R7, #+0]
\ 000000AC C007 LSL R0,R0,#+31
\ 000000AE 0BD5 BPL ??fw_isr_5
315 {
316 AT91F_UDP_EpClear( USBDEV_BASE_UDP, FW_EP_CTRL, USBDEV_UDP_TXCOMP );
\ 000000B0 3868 LDR R0,[R7, #+0]
\ 000000B2 0121 MOV R1,#+1
\ 000000B4 8843 BIC R0,R1
\ 000000B6 3860 STR R0,[R7, #+0]
317 if(fw_AskValidateAddress)
\ 000000B8 754F LDR R7,??fw_isr_0+0x44 ;; fw_AskValidateAddress
\ 000000BA 3878 LDRB R0,[R7, #+0]
\ 000000BC 0028 CMP R0,#+0
\ 000000BE 03D0 BEQ ??fw_isr_5
318 {
319 fw_setAddressEnable(fw_AskValidateAddress);
^
Warning[Ta023]: Call to a non __ramfunc function (fw_setAddressEnable) from
within a __ramfunc function
\ 000000C0 ........ _BLF fw_setAddressEnable,??fw_setAddressEnable??rT?CODE_I
320 fw_AskValidateAddress = 0;
\ 000000C4 0020 MOV R0,#+0
\ 000000C6 3870 STRB R0,[R7, #+0]
321 }
322 }
323 /* traitement de la tache */
324 if((fw_deviceState & FW_DS_SETUP))
\ ??fw_isr_5:
\ 000000C8 2078 LDRB R0,[R4, #+0]
\ 000000CA 4007 LSL R0,R0,#+29
\ 000000CC 05D5 BPL ??fw_isr_4
325 {
326 /* if we receive a setup process the command */
327 fw_deviceState &= ~FW_DS_SETUP;
\ 000000CE 2078 LDRB R0,[R4, #+0]
\ 000000D0 FB21 MOV R1,#+251
\ 000000D2 0140 AND R1,R0
\ 000000D4 2170 STRB R1,[R4, #+0]
328 fw_processCommand();
^
Warning[Ta023]: Call to a non __ramfunc function (fw_processCommand) from
within a __ramfunc function
\ 000000D6 ........ _BLF fw_processCommand,??fw_processCommand??rT?CODE_I
329 }
330 }
331
332 /*******************************************/
333 /* (UDP) Endpoint 1 Interrupt : EP BULK IN */
334 /*******************************************/
335 if(_IT_reg_b1 & AT91C_UDP_EPINT1)
\ ??fw_isr_4:
\ 000000DA B007 LSL R0,R6,#+30
\ 000000DC 0CD5 BPL ??fw_isr_6
336 {
337 /* we sent something */
338 /* transfer is already in progress */
339 /* don't mark it again, this INT can be due to a stall */
340 if( AT91F_UDP_EpStatus( USBDEV_BASE_UDP, FW_EP_BULK_IN ) & USBDEV_UDP_TXCOMP )
\ 000000DE 6A48 LDR R0,??fw_isr_0+0x3C ;; 0xfffb0034
\ 000000E0 0068 LDR R0,[R0, #+0]
\ 000000E2 C007 LSL R0,R0,#+31
\ 000000E4 08D5 BPL ??fw_isr_6
341 {
342 AT91F_UDP_EpClear( USBDEV_BASE_UDP, FW_EP_BULK_IN, USBDEV_UDP_TXCOMP );
\ 000000E6 6848 LDR R0,??fw_isr_0+0x3C ;; 0xfffb0034
\ 000000E8 0168 LDR R1,[R0, #+0]
\ 000000EA 0122 MOV R2,#+1
\ 000000EC 9143 BIC R1,R2
\ 000000EE 0160 STR R1,[R0, #+0]
343 _IT_reg_b1 &= ~AT91C_UDP_EPINT1; /* clear interrupt BULK IN */
\ 000000F0 0220 MOV R0,#+2
\ 000000F2 8643 BIC R6,R0
344 fw_mainTxDone();
^
Warning[Ta023]: Call to a non __ramfunc function (fw_mainTxDone) from within a
__ramfunc function
\ 000000F4 ........ _BLF fw_mainTxDone,??fw_mainTxDone??rT?CODE_I
345 }
346 }
347
348 /********************************************/
349 /* (UDP) Endpoint 2 Interrupt : EP BULK OUT */
350 /********************************************/
351 if(_IT_reg_b1 & AT91C_UDP_EPINT2)
\ ??fw_isr_6:
\ 000000F8 7007 LSL R0,R6,#+29
\ 000000FA 03D5 BPL ??fw_isr_7
352 {
353 _IT_reg_b1 &= ~AT91C_UDP_EPINT2; /* clear interrupt BULK OUT */
\ 000000FC 0420 MOV R0,#+4
\ 000000FE 8643 BIC R6,R0
354 fw_mainRxDone();
^
Warning[Ta023]: Call to a non __ramfunc function (fw_mainRxDone) from within a
__ramfunc function
\ 00000100 ........ _BLF fw_mainRxDone,??fw_mainRxDone??rT?CODE_I
355 }
356
357 /******************************/
358 /* (UDP) USB Resume Interrupt */
359 /******************************/
360 if(_IT_reg_b1 & AT91C_UDP_RXRSM)
\ ??fw_isr_7:
\ 00000104 6348 LDR R0,??fw_isr_0+0x48 ;; 0xfffffc30
\ 00000106 6449 LDR R1,??fw_isr_0+0x4C ;; 0xfffffc2c
\ 00000108 644A LDR R2,??fw_isr_0+0x50 ;; 0xfffffc68
\ 0000010A AB01 LSL R3,R5,#+6
\ 0000010C 1E42 TST R6,R3
\ 0000010E 3FD0 BEQ ??fw_isr_8
361 {
362 USB_EVENT |= USB_EVENT_MASK_RESUME;
\ 00000110 5A4F LDR R7,??fw_isr_0+0x30 ;; USB_EVENT
\ 00000112 BC46 MOV R12,R7
\ 00000114 594B LDR R3,??fw_isr_0+0x30 ;; USB_EVENT
\ 00000116 1F78 LDRB R7,[R3, #+0]
\ 00000118 0223 MOV R3,#+2
\ 0000011A 3B43 ORR R3,R7
\ 0000011C 6746 MOV R7,R12
\ 0000011E 3B70 STRB R3,[R7, #+0]
363
364 AT91F_UDP_DisableIt( USBDEV_BASE_UDP, DISABLE_ALL_IT );
\ 00000120 504B LDR R3,??fw_isr_0+0x18 ;; 0xfffb0014
\ 00000122 514F LDR R7,??fw_isr_0+0x1C ;; 0x2f0f
\ 00000124 1F60 STR R7,[R3, #+0]
365 AT91F_UDP_InterruptClearRegister( USBDEV_BASE_UDP, CLEAR_ALL_IT );
\ 00000126 514B LDR R3,??fw_isr_0+0x20 ;; 0xfffb0020
\ 00000128 FC27 MOV R7,#+252
\ 0000012A BF01 LSL R7,R7,#+6 ;; #+16128
\ 0000012C 1F60 STR R7,[R3, #+0]
366 AT91F_UDP_EnableIt( USBDEV_BASE_UDP, AT91C_UDP_EPINT0 | AT91C_UDP_EPINT1
367 | AT91C_UDP_EPINT2 | AT91C_UDP_RXSUSP
368 | AT91C_UDP_RXRSM | AT91C_UDP_EXTRSM
369 | AT91C_UDP_SOFINT | AT91C_UDP_WAKEUP );
\ 0000012E 504B LDR R3,??fw_isr_0+0x24 ;; 0xfffb0010
\ 00000130 5B4F LDR R7,??fw_isr_0+0x54 ;; 0x2f07
\ 00000132 1F60 STR R7,[R3, #+0]
370
371 #ifndef AT91SAM9265
372 /*************************************************************/
373 /* from AT91C_MASTER_CLOCK=32kHz to AT91C_MASTER_CLOCK=48MHz */
374 /*************************************************************/
375 #ifdef USE_LED
376 AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, (1 << AT91C_ID_PWMC) );
\ 00000134 5B4B LDR R3,??fw_isr_0+0x58 ;; 0xfffffc10
\ 00000136 EF01 LSL R7,R5,#+7
\ 00000138 1F60 STR R7,[R3, #+0]
377 #endif
378 AT91F_PMC_CfgSysClkEnableReg( AT91C_BASE_PMC, AT91C_PMC_UDP );
\ 0000013A 5B4B LDR R3,??fw_isr_0+0x5C ;; 0xfffffc00
\ 0000013C 8027 MOV R7,#+128
\ 0000013E 1F60 STR R7,[R3, #+0]
379
380 #ifndef AT91SAM9265
381 AT91F_UDP_EnableTransceiver(USBDEV_BASE_UDP);
\ 00000140 5A4F LDR R7,??fw_isr_0+0x60 ;; 0xfffb0074
\ 00000142 BC46 MOV R12,R7
\ 00000144 3F68 LDR R7,[R7, #+0]
\ 00000146 5A4B LDR R3,??fw_isr_0+0x64 ;; 0xfffffeff
\ 00000148 3B40 AND R3,R7
\ 0000014A 6746 MOV R7,R12
\ 0000014C 3B60 STR R3,[R7, #+0]
382 #endif
383
384 #if defined (AT91SAM9265) || defined (AT91SAM7A3)
385 #else
386 // Voltage regulator in normal mode : Disable VREG Low Power Mode
387 AT91F_VREG_Disable_LowPowerMode( AT91C_BASE_VREG );
\ 0000014E 594F LDR R7,??fw_isr_0+0x68 ;; 0xfffffd60
\ 00000150 BC46 MOV R12,R7
\ 00000152 3B68 LDR R3,[R7, #+0]
\ 00000154 0127 MOV R7,#+1
\ 00000156 BB43 BIC R3,R7
\ 00000158 6746 MOV R7,R12
\ 0000015A 3B60 STR R3,[R7, #+0]
388 #endif
389
390 // enable Main Oscillator
391 pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
\ 0000015C 564B LDR R3,??fw_isr_0+0x6C ;; 0xfffffc20
\ 0000015E 574F LDR R7,??fw_isr_0+0x70 ;; 0x601
\ 00000160 1F60 STR R7,[R3, #+0]
392 while( !( AT91F_PMC_GetStatus( AT91C_BASE_PMC ) & AT91C_PMC_MOSCS ) );
\ ??fw_isr_9:
\ 00000162 1368 LDR R3,[R2, #+0]
\ 00000164 DB07 LSL R3,R3,#+31
\ 00000166 FCD5 BPL ??fw_isr_9
393
394 AT91F_CKGR_CfgPLLReg( AT91C_BASE_CKGR,
395 ((AT91C_CKGR_DIV & 0x0E) | // for certif
396 (AT91C_CKGR_PLLCOUNT & (28<<8)) |
397 (AT91C_CKGR_MUL & (0x48<<16))) |
398 AT91C_CKGR_USBDIV_1 );
\ 00000168 554B LDR R3,??fw_isr_0+0x74 ;; 0x10481c0e
\ 0000016A 0B60 STR R3,[R1, #+0]
399 while( !( AT91F_PMC_GetStatus( AT91C_BASE_PMC ) & AT91C_PMC_LOCK ) );
\ ??fw_isr_10:
\ 0000016C 1368 LDR R3,[R2, #+0]
\ 0000016E 5B07 LSL R3,R3,#+29
\ 00000170 FCD5 BPL ??fw_isr_10
400 while( !( AT91F_PMC_GetStatus( AT91C_BASE_PMC ) & AT91C_PMC_MCKRDY ) );
\ ??fw_isr_11:
\ 00000172 1368 LDR R3,[R2, #+0]
\ 00000174 2B42 TST R3,R5
\ 00000176 FCD0 BEQ ??fw_isr_11
401
402 // AT91C_MASTER_CLOCK=SLCK/2 : change prescaler first
403 AT91F_PMC_CfgMCKReg( AT91C_BASE_PMC, AT91C_PMC_PRES_CLK_2 );
\ 00000178 0423 MOV R3,#+4
\ 0000017A 0360 STR R3,[R0, #+0]
404 while( !( AT91F_PMC_GetStatus( AT91C_BASE_PMC ) & AT91C_PMC_MCKRDY ) );
\ ??fw_isr_12:
\ 0000017C 1368 LDR R3,[R2, #+0]
\ 0000017E 2B42 TST R3,R5
\ 00000180 FCD0 BEQ ??fw_isr_12
405
406 // AT91C_MASTER_CLOCK=PLLCK/2 : then change source
407 pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
\ 00000182 0368 LDR R3,[R0, #+0]
\ 00000184 0327 MOV R7,#+3
\ 00000186 1F43 ORR R7,R3
\ 00000188 0760 STR R7,[R0, #+0]
408 while( !( AT91F_PMC_GetStatus( AT91C_BASE_PMC ) & AT91C_PMC_MCKRDY ) );
\ ??fw_isr_13:
\ 0000018A 1368 LDR R3,[R2, #+0]
\ 0000018C 2B42 TST R3,R5
\ 0000018E FCD0 BEQ ??fw_isr_13
\ ??fw_isr_8:
\ 00000190 6B01 LSL R3,R5,#+5
\ 00000192 1E42 TST R6,R3
\ 00000194 33D0 BEQ ??fw_isr_2
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