📄 cstartup.lst
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154 00000054 ;-------------------------------
155 00000054 BC009FE5 ldr r0, =__iramend
156 00000058
157 00000058 ;- Set up Fast Interrupt Mode and set FIQ Mode
Stack
158 00000058 D1F021E3 msr CPSR_c, #ARM_MODE_FIQ | I_BIT |
F_BIT
159 0000005C
160 0000005C ;- Init the FIQ register
161 0000005C BC809FE5 ldr r8, =AT91C_BASE_AIC
162 00000060
163 00000060 ;- Set up Interrupt Mode and set IRQ Mode
Stack
164 00000060 D2F021E3 msr CPSR_c, #ARM_MODE_IRQ | I_BIT |
F_BIT
165 00000064 00D0A0E1 mov r13, r0 ; Init
stack IRQ
166 00000068 600040E2 sub r0, r0, #IRQ_STACK_SIZE
167 0000006C
168 0000006C ;- Enable interrupt & Set up Supervisor Mode and
set Supervisor Mode Stack
169 0000006C 13F021E3 msr CPSR_c, #ARM_MODE_SVC
170 00000070 00D0A0E1 mov r13, r0
171 00000074
172 00000074
173 00000074 ;-----------------------------------------------
----------------
174 00000074 ; ?CSTARTUP
175 00000074 ;-----------------------------------------------
----------------
176 00000000 EXTERN __segment_init
177 00000000 EXTERN main
178 00000074 ; Initialize segments.
179 00000074 ; __segment_init is assumed to use
180 00000074 ; instruction set and to be reachable by BL from
the ICODE segment
181 00000074 ; (it is safest to link them in segment
ICODE).
182 00000074 A8009FE5 ldr r0, =__segment_init
183 00000078 0FE0A0E1 mov lr, pc
184 0000007C 10FF2FE1 bx r0
185 00000080
186 00000000 PUBLIC __main
187 00000080 ?jump_to_main:
188 00000080 A0E09FE5 ldr lr, =?call_exit
189 00000084 A0009FE5 ldr r0, =main
190 00000088 __main:
191 00000088 10FF2FE1 bx r0
192 0000008C
193 0000008C ;-----------------------------------------------
-------------------------------
194 0000008C ;- Loop for ever
195 0000008C ;---------------
196 0000008C ;- End of application. Normally, never
occur.
197 0000008C ;- Could jump on Software Reset ( B 0x0
).
198 0000008C ;-----------------------------------------------
-------------------------------
199 0000008C ?call_exit:
200 0000008C End
201 0000008C FEFFFFEA b End
202 00000090
203 00000090
204 00000090 ;-----------------------------------------------
-------------------------------
205 00000090 ;- Manage exception
206 00000090 ;---------------
207 00000090 ;- This module The exception must be ensure in
ARM mode
208 00000090 ;-----------------------------------------------
-------------------------------
209 00000090 ;-----------------------------------------------
-------------------------------
210 00000090 ;- Function : IRQ_Handler_Entry
211 00000090 ;- Treatments : IRQ Controller
Interrupt Handler.
212 00000090 ;- Called Functions : AIC_IVR[interrupt]
213 00000090 ;-----------------------------------------------
-------------------------------
214 00000090 IRQ_Handler_Entry:
215 00000090
216 00000090 ;- Manage Exception Entry
217 00000090 ;- Adjust and save LR_irq in IRQ stack
218 00000090 04E04EE2 sub lr, lr, #4
219 00000094 00402DE9 stmfd sp!, {lr}
220 00000098
221 00000098 ;- Save SPSR need to be saved for nested
interrupt
222 00000098 00E04FE1 mrs r14, SPSR
223 0000009C 00402DE9 stmfd sp!, {r14}
224 000000A0
225 000000A0 ;- Save and r0 in IRQ stack
226 000000A0 01002DE9 stmfd sp!, {r0}
227 000000A4
228 000000A4 ;- Write in the IVR to support Protect
Mode
229 000000A4 ;- No effect in Normal Mode
230 000000A4 ;- De-assert the NIRQ and clear the source in
Protect Mode
231 000000A4 74E09FE5 ldr r14, =AT91C_BASE_AIC
232 000000A8 00019EE5 ldr r0 , [r14, #AIC_IVR]
233 000000AC 00E18EE5 str r14, [r14, #AIC_IVR]
234 000000B0
235 000000B0 ;- Enable Interrupt and Switch in Supervisor
Mode
236 000000B0 13F021E3 msr CPSR_c, #ARM_MODE_SVC
237 000000B4
238 000000B4 ;- Save scratch/used registers and LR in User
Stack
239 000000B4 0E502DE9 stmfd sp!, { r1-r3, r12, r14}
240 000000B8
241 000000B8 ;- Branch to the routine pointed by the
AIC_IVR
242 000000B8 0FE0A0E1 mov r14, pc
243 000000BC 10FF2FE1 bx r0
244 000000C0
245 000000C0 ;- Restore scratch/used registers and LR from
User Stack
246 000000C0 0E50BDE8 ldmia sp!, { r1-r3, r12, r14}
247 000000C4
248 000000C4 ;- Disable Interrupt and switch back in IRQ
mode
249 000000C4 92F021E3 msr CPSR_c, #I_BIT | ARM_MODE_IRQ
250 000000C8
251 000000C8 ;- Mark the End of Interrupt on the AIC
252 000000C8 50E09FE5 ldr r14, =AT91C_BASE_AIC
253 000000CC 30E18EE5 str r14, [r14, #AIC_EOICR]
254 000000D0
255 000000D0 ;- Restore R0
256 000000D0 0100BDE8 ldmia sp!, {r0}
257 000000D4
258 000000D4 ;- Restore SPSR_irq and r0 from IRQ stack
259 000000D4 0040BDE8 ldmia sp!, {r14}
260 000000D8 0EF06FE1 msr SPSR_cxsf, r14
261 000000DC
262 000000DC ;- Restore adjusted LR_irq from IRQ stack
directly in the PC
263 000000DC 0080FDE8 ldmia sp!, {pc}^
264 000000E0
265 000000E0 ;-----------------------------------------------
----------------
266 000000E0 ; ?EXEPTION_VECTOR
267 000000E0 ; This module is only linked if needed for
closing files.
268 000000E0 ;-----------------------------------------------
----------------
269 00000000 PUBLIC AT91F_Default_FIQ_handler
270 00000000 PUBLIC AT91F_Default_IRQ_handler
271 00000000 PUBLIC AT91F_Spurious_handler
272 000000E0
273 000000E0 CODE32 ; Always ARM mode after exeption
274 000000E0
275 000000E0 AT91F_Default_FIQ_handler
276 000000E0 FEFFFFEA b AT91F_Default_FIQ_handler
277 000000E4
278 000000E4 AT91F_Default_IRQ_handler
279 000000E4 FEFFFFEA b AT91F_Default_IRQ_handler
280 000000E8
281 000000E8 AT91F_Spurious_handler
282 000000E8 FEFFFFEA b AT91F_Spurious_handler
283 000000EC
284 000000EC ;-----------------------------------------------
----------------
285 000000EC ; ?EXEPTION_VECTOR
286 000000EC ; This module is only linked if needed for
closing files.
287 000000EC ;-----------------------------------------------
----------------
288 000000EC #define IRQ_MASK 0x00000080
289 000000EC #define FIQ_MASK 0x00000040
290 000000EC #define INTs_MASK (IRQ_MASK | FIQ_MASK)
291 000000EC
292 000000EC ;-----------------------------------------------
----
293 000000EC ; \fn extern void AT91F_enable_interrupt(void)
294 000000EC ; \brief Enable Core interrupt
295 000000EC ;-----------------------------------------------
----
296 000000EC
297 00000000 PUBLIC AT91F_enable_interrupt
298 000000EC
299 000000EC CODE32 ; Always ARM mode after exeption
300 000000EC
301 000000EC AT91F_enable_interrupt
302 000000EC 00000FE1 mrs r0, CPSR
303 000000F0 C000C0E3 bic r0, r0, #INTs_MASK
304 000000F4 00F021E1 msr CPSR_c, r0
305 000000F8 1EFF2FE1 bx lr
306 000000FC
307 000000FC ;-----------------------------------------------
----
308 000000FC ; \fn extern void AT91F_disable_interrupt(void)
309 000000FC ; \brief Disable Core interrupt
310 000000FC ;-----------------------------------------------
----
311 000000FC
312 00000000 PUBLIC AT91F_disable_interrupt
313 000000FC
314 000000FC CODE32 ; Always ARM mode after exeption
315 000000FC
316 000000FC AT91F_disable_interrupt
317 000000FC 00000FE1 mrs r0, CPSR
318 00000100 C00080E3 orr r0, r0, #INTs_MASK
319 00000104 00F021E1 msr CPSR_c, r0
320 00000108 00000FE1 mrs r0, CPSR
321 0000010C C00010E2 ands r0, r0, #INTs_MASK
322 00000110 F9FFFF0A beq AT91F_disable_interrupt
323 00000114 1EFF2FE1 bx lr
324 00000118
325 00000118 ENDMOD
325.1 00000118 TABLE
325.2 00000118 ........ Reference on line 116,155
325.3 0000011C ........ Reference on line 119
325.4 00000120 00F0FFFF Reference on line 161,231,252
325.5 00000124 ........ Reference on line 182
325.6 00000128 ........ Reference on line 188
325.7 0000012C ........ Reference on line 189
325 00000130 ENDMOD
##############################
# CRC:65DE #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 304 #
##############################
##############################
# CRC:65DE #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 304 #
##############################
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