📄 f34x_msd_msd.lst
字号:
-r High
84 =3 sfr FLSCL = 0xB6; // Flash Scale
85 =3 sfr FLKEY = 0xB7; // Flash Lock and Key
86 =3 sfr IP = 0xB8; // Interrupt Priority
87 =3 sfr CLKMUL = 0xB9; // Clock Multiplier
88 =3 sfr AMX0N = 0xBA; // AMUX0 Negative Channel S
-elect
89 =3 sfr AMX0P = 0xBB; // AMUX0 Positive Channel S
-elect
90 =3 sfr ADC0CF = 0xBC; // ADC0 Configuration
91 =3 sfr ADC0L = 0xBD; // ADC0 Low
92 =3 sfr ADC0H = 0xBE; // ADC0 High
93 =3 sfr SMB0CN = 0xC0; // SMBus Control
94 =3 sfr SMB0CF = 0xC1; // SMBus Configuration
95 =3 sfr SMB0DAT = 0xC2; // SMBus Data
96 =3 sfr ADC0GTL = 0xC3; // ADC0 Greater-Than Compar
-e Low
97 =3 sfr ADC0GTH = 0xC4; // ADC0 Greater-Than Compar
-e High
98 =3 sfr ADC0LTL = 0xC5; // ADC0 Less-Than Compare W
-ord Low
99 =3 sfr ADC0LTH = 0xC6; // ADC0 Less-Than Compare W
-ord High
100 =3 sfr P4 = 0xC7; // Port 4 Latch
101 =3 sfr TMR2CN = 0xC8; // Timer/Counter 2 Control
102 =3 sfr REG0CN = 0xC9; // Voltage Regulator Contro
-l
103 =3 sfr TMR2RLL = 0xCA; // Timer/Counter 2 Reload L
-ow
104 =3 sfr TMR2RLH = 0xCB; // Timer/Counter 2 Reload H
-igh
105 =3 sfr TMR2L = 0xCC; // Timer/Counter 2 Low
106 =3 sfr TMR2H = 0xCD; // Timer/Counter 2 High
107 =3 sfr PSW = 0xD0; // Program Status Word
108 =3 sfr REF0CN = 0xD1; // Voltage Reference Contro
-l
109 =3 sfr SCON1 = 0xD2; // UART1 Control
110 =3 sfr SBUF1 = 0xD3; // UART1 Data Buffer
111 =3 sfr P0SKIP = 0xD4; // Port 0 Skip
112 =3 sfr P1SKIP = 0xD5; // Port 1 Skip
113 =3 sfr P2SKIP = 0xD6; // Port 2 Skip
114 =3 sfr USB0XCN = 0xD7; // USB0 Transceiver Control
115 =3 sfr PCA0CN = 0xD8; // PCA0 Control
116 =3 sfr PCA0MD = 0xD9; // PCA0 Mode
117 =3 sfr PCA0CPM0 = 0xDA; // PCA0 Module 0 Mode Regis
-ter
118 =3 sfr PCA0CPM1 = 0xDB; // PCA0 Module 1 Mode Regis
-ter
119 =3 sfr PCA0CPM2 = 0xDC; // PCA0 Module 2 Mode Regis
-ter
120 =3 sfr PCA0CPM3 = 0xDD; // PCA0 Module 3 Mode Regis
-ter
121 =3 sfr PCA0CPM4 = 0xDE; // PCA0 Module 4 Mode Regis
-ter
122 =3 sfr P3SKIP = 0xDF; // Port 3 Skip
123 =3 sfr ACC = 0xE0; // Accumulator
124 =3 sfr XBR0 = 0xE1; // Port I/O Crossbar Contro
C51 COMPILER V7.50 F34X_MSD_MSD 11/28/2006 10:54:20 PAGE 6
-l 0
125 =3 sfr XBR1 = 0xE2; // Port I/O Crossbar Contro
-l 1
126 =3 sfr XBR2 = 0xE3; // Port I/O Crossbar Contro
-l 2
127 =3 sfr IT01CF = 0xE4; // INT0/INT1 Configuration
128 =3 sfr SMOD1 = 0xE5; // UART1 Mode
129 =3 sfr EIE1 = 0xE6; // Extended Interrupt Enabl
-e 1
130 =3 sfr EIE2 = 0xE7; // Extended Interrupt Enabl
-e 2
131 =3 sfr ADC0CN = 0xE8; // ADC0 Control
132 =3 sfr PCA0CPL1 = 0xE9; // PCA0 Capture 1 Low
133 =3 sfr PCA0CPH1 = 0xEA; // PCA0 Capture 1 High
134 =3 sfr PCA0CPL2 = 0xEB; // PCA0 Capture 2 Low
135 =3 sfr PCA0CPH2 = 0xEC; // PCA0 Capture 2 High
136 =3 sfr PCA0CPL3 = 0xED; // PCA0 Capture 3 Low
137 =3 sfr PCA0CPH3 = 0xEE; // PCA0 Capture 3 High
138 =3 sfr RSTSRC = 0xEF; // Reset Source Configurati
-on/Status
139 =3 sfr B = 0xF0; // B Register
140 =3 sfr P0MDIN = 0xF1; // Port 0 Input Mode Config
-uration
141 =3 sfr P1MDIN = 0xF2; // Port 1 Input Mode Config
-uration
142 =3 sfr P2MDIN = 0xF3; // Port 2 Input Mode Config
-uration
143 =3 sfr P3MDIN = 0xF4; // Port 3 Input Mode Config
-uration
144 =3 sfr P4MDIN = 0xF5; // Port 4 Input Mode Config
-uration
145 =3 sfr EIP1 = 0xF6; // Extended Interrupt Prior
-ity 1
146 =3 sfr EIP2 = 0xF7; // Extended Interrupt Prior
-ity 2
147 =3 sfr SPI0CN = 0xF8; // SPI0 Control
148 =3 sfr PCA0L = 0xF9; // PCA0 Counter Low
149 =3 sfr PCA0H = 0xFA; // PCA0 Counter High
150 =3 sfr PCA0CPL0 = 0xFB; // PCA0 Capture 0 Low
151 =3 sfr PCA0CPH0 = 0xFC; // PCA0 Capture 0 High
152 =3 sfr PCA0CPL4 = 0xFD; // PCA0 Capture 4 Low
153 =3 sfr PCA0CPH4 = 0xFE; // PCA0 Capture 4 High
154 =3 sfr VDM0CN = 0xFF; // VDD Monitor Control
155 =3
156 =3
157 =3 //----------------------------------------------------------------
--------------
158 =3 // Bit Definitions
159 =3 //----------------------------------------------------------------
--------------
160 =3
161 =3 // TCON 0x88
162 =3 sbit TF1 = 0x8F; // Timer1 overflow flag
163 =3 sbit TR1 = 0x8E; // Timer1 on/off control
164 =3 sbit TF0 = 0x8D; // Timer0 overflow flag
165 =3 sbit TR0 = 0x8C; // Timer0 on/off control
166 =3 sbit IE1 = 0x8B; // Ext interrupt 1 edge fla
-g
167 =3 sbit IT1 = 0x8A; // Ext interrupt 1 type
168 =3 sbit IE0 = 0x89; // Ext interrupt 0 edge fla
-g
169 =3 sbit IT0 = 0x88; // Ext interrupt 0 type
C51 COMPILER V7.50 F34X_MSD_MSD 11/28/2006 10:54:20 PAGE 7
170 =3
171 =3 // SCON0 0x98
172 =3 sbit S0MODE = 0x9F; // Serial mode control bit
-0
173 =3 // Bit6 UNUSED
174 =3 sbit MCE0 = 0x9D; // Multiprocessor communica
-tion enable
175 =3 sbit REN0 = 0x9C; // Receive enable
176 =3 sbit TB80 = 0x9B; // Transmit bit 8
177 =3 sbit RB80 = 0x9A; // Receive bit 8
178 =3 sbit TI0 = 0x99; // Transmit interrupt flag
179 =3 sbit RI0 = 0x98; // Receive interrupt flag
180 =3
181 =3 // IE 0xA8
182 =3 sbit EA = 0xAF; // Global interrupt enable
183 =3 sbit ESPI0 = 0xAE; // SPI0 interrupt enable
184 =3 sbit ET2 = 0xAD; // Timer2 interrupt enable
185 =3 sbit ES0 = 0xAC; // UART0 interrupt enable
186 =3 sbit ET1 = 0xAB; // Timer1 interrupt enable
187 =3 sbit EX1 = 0xAA; // External interrupt 1 ena
-ble
188 =3 sbit ET0 = 0xA9; // Timer0 interrupt enable
189 =3 sbit EX0 = 0xA8; // External interrupt 0 ena
-ble
190 =3
191 =3 // IP 0xB8
192 =3 // Bit7 UNUSED
193 =3 sbit PSPI0 = 0xBE; // SPI0 interrupt priority
194 =3 sbit PT2 = 0xBD; // Timer2 priority
195 =3 sbit PS0 = 0xBC; // UART0 priority
196 =3 sbit PT1 = 0xBB; // Timer1 priority
197 =3 sbit PX1 = 0xBA; // External interrupt 1 pri
-ority
198 =3 sbit PT0 = 0xB9; // Timer0 priority
199 =3 sbit PX0 = 0xB8; // External interrupt 0 pri
-ority
200 =3
201 =3 // SMB0CN 0xC0
202 =3 sbit MASTER = 0xC7; // Master/slave indicator
203 =3 sbit TXMODE = 0xC6; // Transmit mode indicator
204 =3 sbit STA = 0xC5; // Start flag
205 =3 sbit STO = 0xC4; // Stop flag
206 =3 sbit ACKRQ = 0xC3; // Acknowledge request
207 =3 sbit ARBLOST = 0xC2; // Arbitration lost indicat
-or
208 =3 sbit ACK = 0xC1; // Acknowledge flag
209 =3 sbit SI = 0xC0; // SMBus interrupt flag
210 =3
211 =3 // TMR2CN 0xC8
212 =3 sbit TF2H = 0xCF; // Timer2 high byte overflo
-w flag
213 =3 sbit TF2L = 0xCE; // Timer2 low byte overflow
- flag
214 =3 sbit TF2LEN = 0xCD; // Timer2 low byte interrup
-t enable
215 =3 sbit T2CE = 0xCC; // Timer2 capture enable
216 =3 sbit T2SPLIT = 0xCB; // Timer2 split mode enable
217 =3 sbit TR2 = 0xCA; // Timer2 on/off control
218 =3 sbit T2CSS = 0xC9; // Timer 2 Capture Source s
-elect
219 =3 sbit T2XCLK = 0xC8; // Timer2 external clock se
-lect
C51 COMPILER V7.50 F34X_MSD_MSD 11/28/2006 10:54:20 PAGE 8
220 =3
221 =3 // PSW 0xD0
222 =3 sbit CY = 0xD7; // Carry flag
223 =3 sbit AC = 0xD6; // Auxiliary carry flag
224 =3 sbit F0 = 0xD5; // User flag 0
225 =3 sbit RS1 = 0xD4; // Register bank select 1
226 =3 sbit RS0 = 0xD3; // Register bank select 0
227 =3 sbit OV = 0xD2; // Overflow flag
228 =3 sbit F1 = 0xD1; // User flag 1
229 =3 sbit P = 0xD0; // Accumulator parity flag
230 =3
231 =3 // PCA0CN 0xD8
232 =3 sbit CF = 0xDF; // PCA0 counter overflow fl
-ag
233 =3 sbit CR = 0xDE; // PCA0 counter run control
234 =3 // Bit5 UNUSED
235 =3 sbit CCF4 = 0xDC; // PCA0 module4 capture/com
-pare flag
236 =3 sbit CCF3 = 0xDB; // PCA0 module3 capture/com
-pare flag
237 =3 sbit CCF2 = 0xDA; // PCA0 module2 capture/com
-pare flag
238 =3 sbit CCF1 = 0xD9; // PCA0 module1 capture/com
-pare flag
239 =3 sbit CCF0 = 0xD8; // PCA0 module0 capture/com
-pare flag
240 =3
241 =3 // ADC0CN 0xE8
242 =3 sbit AD0EN = 0xEF; // ADC0 enable
243 =3 sbit AD0TM = 0xEE; // ADC0 track mode
244 =3 sbit AD0INT = 0xED; // ADC0 conversion complete
- interrupt flag
245 =3 sbit AD0BUSY = 0xEC; // ADC0 busy flag
246 =3 sbit AD0WINT = 0xEB; // ADC0 window compare inte
-rrupt flag
247 =3 sbit AD0CM2 = 0xEA; // ADC0 conversion mode sel
-ect 2
248 =3 sbit AD0CM1 = 0xE9; // ADC0 conversion mode sel
-ect 1
249 =3 sbit AD0CM0 = 0xE8; // ADC0 conversion mode sel
-ect 0
250 =3
251 =3 // SPI0CN 0xF8
252 =3 sbit SPIF = 0xFF; // SPI0 interrupt flag
253 =3 sbit WCOL = 0xFE; // SPI0 write collision fla
-g
254 =3 sbit MODF = 0xFD; // SPI0 mode fault flag
255 =3 sbit RXOVRN = 0xFC; // SPI0 rx overrun flag
256 =3 sbit NSSMD1 = 0xFB; // SPI0 slave select mode 1
257 =3 sbit NSSMD0 = 0xFA; // SPI0 slave select mode 0
258 =3 sbit TXBMT = 0xF9; // SPI0 transmit buffer emp
-ty
259 =3 sbit SPIEN = 0xF8; // SPI0 SPI enable
260 =3
261 =3
262 =3 //----------------------------------------------------------------
--------------
263 =3 // Interrupt Priorities
264 =3 //----------------------------------------------------------------
--------------
265 =3
266 =3 #define INTERRUPT_INT0 0 // External Interrupt 0
C51 COMPILER V7.50 F34X_MSD_MSD 11/28/2006 10:54:20 PAGE 9
267 =3 #define INTERRUPT_TIMER0 1 // Timer0 Overflow
268 =3 #define INTERRUPT_INT1 2 // External Interrupt 1
269 =3 #define INTERRUPT_TIMER1 3 // Timer1 Overflow
270 =3 #define INTERRUPT_UART0 4 // Serial Port 0
271 =3 #define INTERRUPT_TIMER2 5 // Timer2 Overflow
272 =3 #define INTERRUPT_SPI0 6 // Serial Peripheral Interf
-ace 0
273 =3 #define INTERRUPT_SMBUS0 7 // SMBus0 Interface
274 =3 #define INTERRUPT_USB0 8 // USB Interface
275 =3 #define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
276 =3 #define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
277 =3 #define INTERRUPT_PCA0 11 // PCA0 Peripheral
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