f34x_msd_mmc.lst

USB读写SD卡例程

C51 COMPILER V7.50   F34X_MSD_MMC                  11/28/2006 10:54:17 PAGE 1   


C51 COMPILER V7.50, COMPILATION OF MODULE F34X_MSD_MMC
OBJECT MODULE PLACED IN F34x_MSD_MMC.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\c51.exe F34x_MSD_MMC.c PW(80) SB LC OT(9,SI
                    -ZE) CD DB OE DF(__F340_VER__) LARGE

line level    source

   1          //----------------------------------------------------------------
             --------------
   2          // F34x_MSD_MMC.c
   3          //----------------------------------------------------------------
             --------------
   4          // Copyright 2006 Silicon Laboratories, Inc.
   5          // http://www.silabs.com
   6          //
   7          // Program Description:
   8          //
   9          // MMC FLASH is used for storing the log entries.  Each entry cont
             -ains
  10          // the temperature in hundredths of a degree C, the day, hour, min
             -ute, and
  11          // second that the reading was taken.  The LogUpdate function stor
             -es log
  12          // entries in an external memory buffer and then writes that buffe
             -r out to the
  13          // MMC when it is full.  Communication with the MMC is performed t
             -hrough the 
  14          // MMC access functions.  These functions provide transparent MMC 
             -access to 
  15          // the higher level functions (Logging functions).  The MMC interf
             -ace is broken
  16          // into two pieces.  The high level piece consists of the user cal
             -lable MMC
  17          // access functions (MMC_FLASH_Read, MMC_FLASH_Write, MMC_FLASH_Cl
             -ear, 
  18          // MMC_FLASH_MassErase).  These functions are called by the user t
             -o execute
  19          // data operations on the MMC.  They break down the data operation
             -s into MMC
  20          // commands.  The low level piece consists of a single command exe
             -cution
  21          // function (MMC_Command_Exec) which is called by the MMC data man
             -ipulation
  22          // functions.  This function is called every time a command must b
             -e sent to the
  23          // MMC.  It handles all of the required SPI traffic between the Si
             -licon 
  24          // Laboratories device and the MMC.
  25          //
  26          //
  27          // How To Test:    See Readme.txt
  28          //
  29          //
  30          // FID:            34X000043
  31          // Target:         C8051F34x
  32          // Tool chain:     Keil
  33          // Command Line:   See Readme.txt
  34          // Project Name:   F34x_USB_MSD
  35          //
  36          // Release 1.1
  37          //    -All changes by PKC
C51 COMPILER V7.50   F34X_MSD_MMC                  11/28/2006 10:54:17 PAGE 2   

  38          //    -09 JUN 2006
  39          //    -Replaced SFR definitions file "c8051f320.h" with "c8051f340
             -.h"
  40          //    -Corrected "SPIDAT" to "SPI0DAT" in function Write_Read_Spi_
             -Byte
  41          //
  42          // Release 1.0
  43          //    -Initial Release
  44          //
  45          
  46          
  47          //----------------------------------------------------------------
             --------------
  48          // Includes
  49          //----------------------------------------------------------------
             --------------
  50          
  51          #include "F34x_MSD_Definitions.h"
   1      =1  //----------------------------------------------------------------
             --------------
   2      =1  // F34x_MSD_Definitions.h
   3      =1  //----------------------------------------------------------------
             --------------
   4      =1  // Copyright 2006 Silicon Laboratories, Inc.
   5      =1  // http://www.silabs.com
   6      =1  //
   7      =1  // Program Description:
   8      =1  //
   9      =1  // Header file with all definitions.
  10      =1  //
  11      =1  //
  12      =1  // FID:            34X000032
  13      =1  // Target:         C8051F34x
  14      =1  // Tool chain:     Keil
  15      =1  // Command Line:   See Readme.txt
  16      =1  // Project Name:   F34x_USB_MSD
  17      =1  //
  18      =1  // Release 1.1
  19      =1  //    -All changes by PKC
  20      =1  //    -09 JUN 2006
  21      =1  //    -Replaced SFR definitions file "c8051f320.h" with "c8051f340
             -.h"
  22      =1  //
  23      =1  // Release 1.0
  24      =1  //    -Initial Release
  25      =1  //
  26      =1  
  27      =1  //----------------------------------------------------------------
             --------------
  28      =1  // Header File Preprocessor Directive
  29      =1  //----------------------------------------------------------------
             --------------
  30      =1  
  31      =1  #ifndef __DEFINITIONS_H__
  32      =1  #define __DEFINITIONS_H__
  33      =1  
  34      =1  #define DEBUG_TIMEOUTS
  35      =1  #include "c8051f340.h"
   1      =2  //----------------------------------------------------------------
             --------------
   2      =2  // C8051F340.h
   3      =2  //----------------------------------------------------------------
C51 COMPILER V7.50   F34X_MSD_MMC                  11/28/2006 10:54:17 PAGE 3   

             --------------
   4      =2  // Copyright 2005 Silicon Laboratories, Inc.
   5      =2  // http://www.silabs.com
   6      =2  //
   7      =2  // Program Description:
   8      =2  //
   9      =2  // Register/bit definitions for the C8051F34x family.
  10      =2  //
  11      =2  //
  12      =2  // FID:            34X000002
  13      =2  // Target:         C8051F340, 'F341, 'F342, 'F343, 'F344, 'F345, '
             -F346, 'F347
  14      =2  // Tool chain:     Keil
  15      =2  // Command Line:   None
  16      =2  //
  17      =2  // Release 1.0
  18      =2  //    -Initial Release (GP\PKC)
  19      =2  //    -13 DEC 2005
  20      =2  
  21      =2  //----------------------------------------------------------------
             --------------
  22      =2  // Header File Preprocessor Directive
  23      =2  //----------------------------------------------------------------
             --------------
  24      =2  
  25      =2  #ifndef C8051F340_H
  26      =2  #define C8051F340_H
  27      =2  
  28      =2  //----------------------------------------------------------------
             --------------
  29      =2  // Byte Registers
  30      =2  //----------------------------------------------------------------
             --------------
  31      =2  
  32      =2  sfr  P0           =  0x80;             // Port 0 Latch
  33      =2  sfr  SP           =  0x81;             // Stack Pointer
  34      =2  sfr  DPL          =  0x82;             // Data Pointer Low
  35      =2  sfr  DPH          =  0x83;             // Data Pointer High
  36      =2  sfr  EMI0TC       =  0x84;             // EMIF Timing
  37      =2  sfr  EMI0CF       =  0x85;             // EMIF Configuration
  38      =2  sfr  OSCLCN       =  0x86;             // Internal Low-Freq Oscill
             -ator Control
  39      =2  sfr  PCON         =  0x87;             // Power Control
  40      =2  sfr  TCON         =  0x88;             // Timer/Counter Control
  41      =2  sfr  TMOD         =  0x89;             // Timer/Counter Mode
  42      =2  sfr  TL0          =  0x8A;             // Timer/Counter 0 Low
  43      =2  sfr  TL1          =  0x8B;             // Timer/Counter 1 Low
  44      =2  sfr  TH0          =  0x8C;             // Timer/Counter 0 High
  45      =2  sfr  TH1          =  0x8D;             // Timer/Counter 1 High
  46      =2  sfr  CKCON        =  0x8E;             // Clock Control
  47      =2  sfr  PSCTL        =  0x8F;             // Program Store R/W Contro
             -l
  48      =2  sfr  P1           =  0x90;             // Port 1 Latch
  49      =2  sfr  TMR3CN       =  0x91;             // Timer/Counter 3Control
  50      =2  sfr  TMR3RLL      =  0x92;             // Timer/Counter 3 Reload L
             -ow
  51      =2  sfr  TMR3RLH      =  0x93;             // Timer/Counter 3 Reload H
             -igh
  52      =2  sfr  TMR3L        =  0x94;             // Timer/Counter 3Low
  53      =2  sfr  TMR3H        =  0x95;             // Timer/Counter 3 High
  54      =2  sfr  USB0ADR      =  0x96;             // USB0 Indirect Address Re
             -gister
C51 COMPILER V7.50   F34X_MSD_MMC                  11/28/2006 10:54:17 PAGE 4   

  55      =2  sfr  USB0DAT      =  0x97;             // USB0 Data Register
  56      =2  sfr  SCON0        =  0x98;             // UART0 Control
  57      =2  sfr  SBUF0        =  0x99;             // UART0 Data Buffer
  58      =2  sfr  CPT1CN       =  0x9A;             // Comparator1 Control
  59      =2  sfr  CPT0CN       =  0x9B;             // Comparator0 Control
  60      =2  sfr  CPT1MD       =  0x9C;             // Comparator1 Mode Selecti
             -on
  61      =2  sfr  CPT0MD       =  0x9D;             // Comparator0 Mode Selecti
             -on
  62      =2  sfr  CPT1MX       =  0x9E;             // Comparator1 MUX Selectio
             -n
  63      =2  sfr  CPT0MX       =  0x9F;             // Comparator0 MUX Selectio
             -n
  64      =2  sfr  P2           =  0xA0;             // Port 2 Latch
  65      =2  sfr  SPI0CFG      =  0xA1;             // SPI Configuration
  66      =2  sfr  SPI0CKR      =  0xA2;             // SPI Clock Rate Control
  67      =2  sfr  SPI0DAT      =  0xA3;             // SPI Data
  68      =2  sfr  P0MDOUT      =  0xA4;             // Port 0 Output Mode Confi
             -guration
  69      =2  sfr  P1MDOUT      =  0xA5;             // Port 1 Output Mode Confi
             -guration
  70      =2  sfr  P2MDOUT      =  0xA6;             // Port 2 Output Mode Confi
             -guration
  71      =2  sfr  P3MDOUT      =  0xA7;             // Port 3 Output Mode Confi
             -guration
  72      =2  sfr  IE           =  0xA8;             // Interrupt Enable
  73      =2  sfr  CLKSEL       =  0xA9;             // Clock Select
  74      =2  sfr  EMI0CN       =  0xAA;             // External Memory Interfac
             -e Control
  75      =2  sfr  SBCON1       =  0xAC;             // UART1 Baud Rate Generato
             -r Control
  76      =2  sfr  P4MDOUT      =  0xAE;             // Port 4 Output Mode Confi
             -guration
  77      =2  sfr  PFE0CN       =  0xAF;             // Prefetch Engine Control
  78      =2  sfr  P3           =  0xB0;             // Port 3 Latch
  79      =2  sfr  OSCXCN       =  0xB1;             // External Oscillator Cont
             -rol
  80      =2  sfr  OSCICN       =  0xB2;             // Internal Oscillator Cont
             -rol
  81      =2  sfr  OSCICL       =  0xB3;             // Internal Oscillator Cali
             -bration
  82      =2  sfr  SBRLL1       =  0xB4;             // UART1 Baud Rate Generato
             -r Low
  83      =2  sfr  SBRLH1       =  0xB5;             // UART1 Baud Rate Generato
             -r High
  84      =2  sfr  FLSCL        =  0xB6;             // Flash Scale
  85      =2  sfr  FLKEY        =  0xB7;             // Flash Lock and Key
  86      =2  sfr  IP           =  0xB8;             // Interrupt Priority
  87      =2  sfr  CLKMUL       =  0xB9;             // Clock Multiplier
  88      =2  sfr  AMX0N        =  0xBA;             // AMUX0 Negative Channel S
             -elect
  89      =2  sfr  AMX0P        =  0xBB;             // AMUX0 Positive Channel S
             -elect
  90      =2  sfr  ADC0CF       =  0xBC;             // ADC0 Configuration
  91      =2  sfr  ADC0L        =  0xBD;             // ADC0 Low
  92      =2  sfr  ADC0H        =  0xBE;             // ADC0 High
  93      =2  sfr  SMB0CN       =  0xC0;             // SMBus Control
  94      =2  sfr  SMB0CF       =  0xC1;             // SMBus Configuration
  95      =2  sfr  SMB0DAT      =  0xC2;             // SMBus Data
  96      =2  sfr  ADC0GTL      =  0xC3;             // ADC0 Greater-Than Compar