📄 f34x_msd_usb_procedure.lst
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A51 MACRO ASSEMBLER F34X_MSD_USB_PROCEDURE 11/28/2006 10:54:46 PAGE 1
MACRO ASSEMBLER A51 V7.10
OBJECT MODULE PLACED IN F34x_MSD_USB_Procedure.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.exe F34x_MSD_USB_Procedure.asm XR GEN DB EP NOMOD51
LOC OBJ LINE SOURCE
1 ;//----------------------------------------------------------------------------
2 ;// F34x_MSD_USB_Procedure.asm
3 ;//----------------------------------------------------------------------------
4 ;// Copyright 2006 Silicon Laboratories, Inc.
5 ;// http://www.silabs.com
6 ;//
7 ;// Program Description:
8 ;//
9 ;// This file contains commands for USB interface.
10 ;//
11 ;//
12 ;//
13 ;// How To Test: See Readme.txt
14 ;//
15 ;//
16 ;// FID: 34X000064
17 ;// Target: C8051F34x
18 ;// Tool chain: Keil
19 ;// Command Line: See Readme.txt
20 ;// Project Name: F34x_USB_MSD
21 ;//
22 ;// Release 1.1
23 ;// -All changes by PKC
24 ;// -09 JUN 2006
25 ;// -Removed individual SFR definitions and included c8051f340.inc
26 ;//
27 ;// Release 1.0
28 ;// -Initial Release
29 ;//
30
31 ;$include (c8051f340.inc) ; Include register definition file
+1 32 ;------------------------------------------------------------------------------
+1 33 ; C8051F340.INC
+1 34 ;------------------------------------------------------------------------------
+1 35 ; Copyright 2005 Silicon Laboratories, Inc.
+1 36 ; http://www.silabs.com
+1 37 ;
+1 38 ; Program Description:
+1 39 ;
+1 40 ; Register/bit definitions for the C8051F34x family.
+1 41 ;
+1 42 ;
+1 43 ; FID: 34X000003
+1 44 ; Target: C8051F340, 'F341, 'F342, 'F343, 'F344, 'F345, 'F346, 'F347
+1 45 ; Tool chain: Keil
+1 46 ; Command Line: None
+1 47 ;
+1 48 ; Release 1.0
+1 49 ; -Initial Revision (GP\PKC)
+1 50 ; -13 DEC 2005
+1 51 ;
+1 52
+1 53 ;------------------------------------------------------------------------------
+1 54 ; Byte Registers
+1 55 ;------------------------------------------------------------------------------
+1 56
0080 +1 57 P0 DATA 080H ; Port 0 Latch
0081 +1 58 SP DATA 081H ; Stack Pointer
A51 MACRO ASSEMBLER F34X_MSD_USB_PROCEDURE 11/28/2006 10:54:46 PAGE 2
0082 +1 59 DPL DATA 082H ; Data Pointer Low
0083 +1 60 DPH DATA 083H ; Data Pointer High
0084 +1 61 EMI0TC DATA 084H ; External Memory Interface Timing
0085 +1 62 EMI0CF DATA 085H ; External Memory Interface Config
0086 +1 63 OSCLCN DATA 086H ; Internal Low-Freq Oscillator Control
0087 +1 64 PCON DATA 087H ; Power Control
0088 +1 65 TCON DATA 088H ; Timer/Counter Control
0089 +1 66 TMOD DATA 089H ; Timer/Counter Mode
008A +1 67 TL0 DATA 08AH ; Timer/Counter 0 Low
008B +1 68 TL1 DATA 08BH ; Timer/Counter 1 Low
008C +1 69 TH0 DATA 08CH ; Timer/Counter 0 High
008D +1 70 TH1 DATA 08DH ; Timer/Counter 1 High
008E +1 71 CKCON DATA 08EH ; Clock Control
008F +1 72 PSCTL DATA 08FH ; Program Store R/W Control
0090 +1 73 P1 DATA 090H ; Port 1 Latch
0091 +1 74 TMR3CN DATA 091H ; Timer/Counter 3Control
0092 +1 75 TMR3RLL DATA 092H ; Timer/Counter 3 Reload Low
0093 +1 76 TMR3RLH DATA 093H ; Timer/Counter 3 Reload High
0094 +1 77 TMR3L DATA 094H ; Timer/Counter 3Low
0095 +1 78 TMR3H DATA 095H ; Timer/Counter 3 High
0096 +1 79 USB0ADR DATA 096H ; USB0 Indirect Address Register
0097 +1 80 USB0DAT DATA 097H ; USB0 Data Register
0098 +1 81 SCON0 DATA 098H ; UART0 Control
0099 +1 82 SBUF0 DATA 099H ; UART0 Data Buffer
009A +1 83 CPT1CN DATA 09AH ; Comparator1 Control
009B +1 84 CPT0CN DATA 09BH ; Comparator0 Control
009C +1 85 CPT1MD DATA 09CH ; Comparator1 Mode Selection
009D +1 86 CPT0MD DATA 09DH ; Comparator0 Mode Selection
009E +1 87 CPT1MX DATA 09EH ; Comparator1 MUX Selection
009F +1 88 CPT0MX DATA 09FH ; Comparator0 MUX Selection
00A0 +1 89 P2 DATA 0A0H ; Port 2 Latch
00A1 +1 90 SPI0CFG DATA 0A1H ; SPI Configuration
00A2 +1 91 SPI0CKR DATA 0A2H ; SPI Clock Rate Control
00A3 +1 92 SPI0DAT DATA 0A3H ; SPI Data
00A4 +1 93 P0MDOUT DATA 0A4H ; Port 0 Output Mode Configuration
00A5 +1 94 P1MDOUT DATA 0A5H ; Port 1 Output Mode Configuration
00A6 +1 95 P2MDOUT DATA 0A6H ; Port 2 Output Mode Configuration
00A7 +1 96 P3MDOUT DATA 0A7H ; Port 3 Output Mode Configuration
00A8 +1 97 IE DATA 0A8H ; Interrupt Enable
00A9 +1 98 CLKSEL DATA 0A9H ; Clock Select
00AA +1 99 EMI0CN DATA 0AAH ; External Memory Interface Control
00AC +1 100 SBCON1 DATA 0ACH ; UART1 Baud Rate Generator Control
00AE +1 101 P4MDOUT DATA 0AEH ; Port 4 Output Mode Configuration
00AF +1 102 PFE0CN DATA 0AFH ; Prefetch Engine Control
00B0 +1 103 P3 DATA 0B0H ; Port 3 Latch
00B1 +1 104 OSCXCN DATA 0B1H ; External Oscillator Control
00B2 +1 105 OSCICN DATA 0B2H ; Internal Oscillator Control
00B3 +1 106 OSCICL DATA 0B3H ; Internal Oscillator Calibration
00B4 +1 107 SBRLL1 DATA 0B4H ; UART1 Baud Rate Generator Low
00B5 +1 108 SBRLH1 DATA 0B5H ; UART1 Baud Rate Generator High
00B6 +1 109 FLSCL DATA 0B6H ; Flash Scale
00B7 +1 110 FLKEY DATA 0B7H ; Flash Lock and Key
00B8 +1 111 IP DATA 0B8H ; Interrupt Priority
00B9 +1 112 CLKMUL DATA 0B9H ; Clock Multiplier
00BA +1 113 AMX0N DATA 0BAH ; AMUX0 Negative Channel Select
00BB +1 114 AMX0P DATA 0BBH ; AMUX0 Positive Channel Select
00BC +1 115 ADC0CF DATA 0BCH ; ADC0 Configuration
00BD +1 116 ADC0L DATA 0BDH ; ADC0 Low
00BE +1 117 ADC0H DATA 0BEH ; ADC0 High
00C0 +1 118 SMB0CN DATA 0C0H ; SMBus Control
00C1 +1 119 SMB0CF DATA 0C1H ; SMBus Configuration
00C2 +1 120 SMB0DAT DATA 0C2H ; SMBus Data
00C3 +1 121 ADC0GTL DATA 0C3H ; ADC0 Greater-Than Compare Low
00C4 +1 122 ADC0GTH DATA 0C4H ; ADC0 Greater-Than Compare High
00C5 +1 123 ADC0LTL DATA 0C5H ; ADC0 Less-Than Compare Word Low
00C6 +1 124 ADC0LTH DATA 0C6H ; ADC0 Less-Than Compare Word High
A51 MACRO ASSEMBLER F34X_MSD_USB_PROCEDURE 11/28/2006 10:54:46 PAGE 3
00C7 +1 125 P4 DATA 0C7H ; Port 4 Latch
00C8 +1 126 TMR2CN DATA 0C8H ; Timer/Counter 2 Control
00C9 +1 127 REG0CN DATA 0C9H ; Voltage Regulator Control
00CA +1 128 TMR2RLL DATA 0CAH ; Timer/Counter 2 Reload Low
00CB +1 129 TMR2RLH DATA 0CBH ; Timer/Counter 2 Reload High
00CC +1 130 TMR2L DATA 0CCH ; Timer/Counter 2 Low
00CD +1 131 TMR2H DATA 0CDH ; Timer/Counter 2 High
00D0 +1 132 PSW DATA 0D0H ; Program Status Word
00D1 +1 133 REF0CN DATA 0D1H ; Voltage Reference Control
00D2 +1 134 SCON1 DATA 0D2H ; UART1 Control
00D3 +1 135 SBUF1 DATA 0D3H ; UART1 Data Buffer
00D4 +1 136 P0SKIP DATA 0D4H ; Port 0 Skip
00D5 +1 137 P1SKIP DATA 0D5H ; Port 1 Skip
00D6 +1 138 P2SKIP DATA 0D6H ; Port 2 Skip
00D7 +1 139 USB0XCN DATA 0D7H ; USB0 Transceiver Control
00D8 +1 140 PCA0CN DATA 0D8H ; PCA Control
00D9 +1 141 PCA0MD DATA 0D9H ; PCA Mode
00DA +1 142 PCA0CPM0 DATA 0DAH ; PCA Module 0 Mode Register
00DB +1 143 PCA0CPM1 DATA 0DBH ; PCA Module 1 Mode Register
00DC +1 144 PCA0CPM2 DATA 0DCH ; PCA Module 2 Mode Register
00DD +1 145 PCA0CPM3 DATA 0DDH ; PCA Module 3 Mode Register
00DE +1 146 PCA0CPM4 DATA 0DEH ; PCA Module 4 Mode Register
00DF +1 147 P3SKIP DATA 0DFH ; Port 3Skip
00E0 +1 148 ACC DATA 0E0H ; Accumulator
00E1 +1 149 XBR0 DATA 0E1H ; Port I/O Crossbar Control 0
00E2 +1 150 XBR1 DATA 0E2H ; Port I/O Crossbar Control 1
00E3 +1 151 XBR2 DATA 0E3H ; Port I/O Crossbar Control 2
00E4 +1 152 IT01CF DATA 0E4H ; INT0/INT1 Configuration
00E5 +1 153 SMOD1 DATA 0E5H ; UART1 Mode
00E6 +1 154 EIE1 DATA 0E6H ; Extended Interrupt Enable 1
00E7 +1 155 EIE2 DATA 0E7H ; Extended Interrupt Enable 2
00E8 +1 156 ADC0CN DATA 0E8H ; ADC0 Control
00E9 +1 157 PCA0CPL1 DATA 0E9H ; PCA Capture 1 Low
00EA +1 158 PCA0CPH1 DATA 0EAH ; PCA Capture 1 High
00EB +1 159 PCA0CPL2 DATA 0EBH ; PCA Capture 2 Low
00EC +1 160 PCA0CPH2 DATA 0ECH ; PCA Capture 2 High
00ED +1 161 PCA0CPL3 DATA 0EDH ; PCA Capture 3 Low
00EE +1 162 PCA0CPH3 DATA 0EEH ; PCA Capture 3High
00EF +1 163 RSTSRC DATA 0EFH ; Reset Source Configuration/Status
00F0 +1 164 B DATA 0F0H ; B Register
00F1 +1 165 P0MDIN DATA 0F1H ; Port 0 Input Mode Configuration
00F2 +1 166 P1MDIN DATA 0F2H ; Port 1 Input Mode Configuration
00F3 +1 167 P2MDIN DATA 0F3H ; Port 2 Input Mode Configuration
00F4 +1 168 P3MDIN DATA 0F4H ; Port 3 Input Mode Configuration
00F5 +1 169 P4MDIN DATA 0F5H ; Port 4 Input Mode Configuration
00F6 +1 170 EIP1 DATA 0F6H ; Extended Interrupt Priority 1
00F7 +1 171 EIP2 DATA 0F7H ; Extended Interrupt Priority 2
00F8 +1 172 SPI0CN DATA 0F8H ; SPI Control
00F9 +1 173 PCA0L DATA 0F9H ; PCA Counter Low
00FA +1 174 PCA0H DATA 0FAH ; PCA Counter High
00FB +1 175 PCA0CPL0 DATA 0FBH ; PCA Capture 0 Low
00FC +1 176 PCA0CPH0 DATA 0FCH ; PCA Capture 0 High
00FD +1 177 PCA0CPL4 DATA 0FDH ; PCA Capture 4 Low
00FE +1 178 PCA0CPH4 DATA 0FEH ; PCA Capture 4 High
00FF +1 179 VDM0CN DATA 0FFH ; VDD Monitor Control
+1 180
+1 181 ;------------------------------------------------------------------------------
+1 182 ; Bit Definitions
+1 183 ;------------------------------------------------------------------------------
+1 184
+1 185 ; TCON 088H
008F +1 186 TF1 BIT TCON.7 ; Timer1 overflow flag
008E +1 187 TR1 BIT TCON.6 ; Timer1 on/off control
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