📄 f34x_msd_usb_isr.lst
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=3
=3 // IE 0xA8
=3 sbit EA = 0xAF; // Global interrupt enable
=3 sbit ESPI0 = 0xAE; // SPI0 interrupt enable
=3 sbit ET2 = 0xAD; // Timer2 interrupt enable
=3 sbit ES0 = 0xAC; // UART0 interrupt enable
=3 sbit ET1 = 0xAB; // Timer1 interrupt enable
=3 sbit EX1 = 0xAA; // External interrupt 1 ena
-ble
=3 sbit ET0 = 0xA9; // Timer0 interrupt enable
=3 sbit EX0 = 0xA8; // External interrupt 0 ena
-ble
=3
=3 // IP 0xB8
=3 // Bit7 UNUSED
=3 sbit PSPI0 = 0xBE; // SPI0 interrupt priority
=3 sbit PT2 = 0xBD; // Timer2 priority
=3 sbit PS0 = 0xBC; // UART0 priority
=3 sbit PT1 = 0xBB; // Timer1 priority
=3 sbit PX1 = 0xBA; // External interrupt 1 pri
-ority
=3 sbit PT0 = 0xB9; // Timer0 priority
=3 sbit PX0 = 0xB8; // External interrupt 0 pri
-ority
=3
=3 // SMB0CN 0xC0
=3 sbit MASTER = 0xC7; // Master/slave indicator
=3 sbit TXMODE = 0xC6; // Transmit mode indicator
=3 sbit STA = 0xC5; // Start flag
=3 sbit STO = 0xC4; // Stop flag
=3 sbit ACKRQ = 0xC3; // Acknowledge request
=3 sbit ARBLOST = 0xC2; // Arbitration lost indicat
-or
=3 sbit ACK = 0xC1; // Acknowledge flag
=3 sbit SI = 0xC0; // SMBus interrupt flag
=3
=3 // TMR2CN 0xC8
=3 sbit TF2H = 0xCF; // Timer2 high byte overflo
-w flag
=3 sbit TF2L = 0xCE; // Timer2 low byte overflow
- flag
=3 sbit TF2LEN = 0xCD; // Timer2 low byte interrup
-t enable
=3 sbit T2CE = 0xCC; // Timer2 capture enable
=3 sbit T2SPLIT = 0xCB; // Timer2 split mode enable
=3 sbit TR2 = 0xCA; // Timer2 on/off control
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 14
=3 sbit T2CSS = 0xC9; // Timer 2 Capture Source s
-elect
=3 sbit T2XCLK = 0xC8; // Timer2 external clock se
-lect
=3
=3 // PSW 0xD0
=3 sbit CY = 0xD7; // Carry flag
=3 sbit AC = 0xD6; // Auxiliary carry flag
=3 sbit F0 = 0xD5; // User flag 0
=3 sbit RS1 = 0xD4; // Register bank select 1
=3 sbit RS0 = 0xD3; // Register bank select 0
=3 sbit OV = 0xD2; // Overflow flag
=3 sbit F1 = 0xD1; // User flag 1
=3 sbit P = 0xD0; // Accumulator parity flag
=3
=3 // PCA0CN 0xD8
=3 sbit CF = 0xDF; // PCA0 counter overflow fl
-ag
=3 sbit CR = 0xDE; // PCA0 counter run control
=3 // Bit5 UNUSED
=3 sbit CCF4 = 0xDC; // PCA0 module4 capture/com
-pare flag
=3 sbit CCF3 = 0xDB; // PCA0 module3 capture/com
-pare flag
=3 sbit CCF2 = 0xDA; // PCA0 module2 capture/com
-pare flag
=3 sbit CCF1 = 0xD9; // PCA0 module1 capture/com
-pare flag
=3 sbit CCF0 = 0xD8; // PCA0 module0 capture/com
-pare flag
=3
=3 // ADC0CN 0xE8
=3 sbit AD0EN = 0xEF; // ADC0 enable
=3 sbit AD0TM = 0xEE; // ADC0 track mode
=3 sbit AD0INT = 0xED; // ADC0 conversion complete
- interrupt flag
=3 sbit AD0BUSY = 0xEC; // ADC0 busy flag
=3 sbit AD0WINT = 0xEB; // ADC0 window compare inte
-rrupt flag
=3 sbit AD0CM2 = 0xEA; // ADC0 conversion mode sel
-ect 2
=3 sbit AD0CM1 = 0xE9; // ADC0 conversion mode sel
-ect 1
=3 sbit AD0CM0 = 0xE8; // ADC0 conversion mode sel
-ect 0
=3
=3 // SPI0CN 0xF8
=3 sbit SPIF = 0xFF; // SPI0 interrupt flag
=3 sbit WCOL = 0xFE; // SPI0 write collision fla
-g
=3 sbit MODF = 0xFD; // SPI0 mode fault flag
=3 sbit RXOVRN = 0xFC; // SPI0 rx overrun flag
=3 sbit NSSMD1 = 0xFB; // SPI0 slave select mode 1
=3 sbit NSSMD0 = 0xFA; // SPI0 slave select mode 0
=3 sbit TXBMT = 0xF9; // SPI0 transmit buffer emp
-ty
=3 sbit SPIEN = 0xF8; // SPI0 SPI enable
=3
=3
=3 //----------------------------------------------------------------
--------------
=3 // Interrupt Priorities
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 15
=3 //----------------------------------------------------------------
--------------
=3
=3 #define INTERRUPT_INT0 0 // External Interrupt 0
=3 #define INTERRUPT_TIMER0 1 // Timer0 Overflow
=3 #define INTERRUPT_INT1 2 // External Interrupt 1
=3 #define INTERRUPT_TIMER1 3 // Timer1 Overflow
=3 #define INTERRUPT_UART0 4 // Serial Port 0
=3 #define INTERRUPT_TIMER2 5 // Timer2 Overflow
=3 #define INTERRUPT_SPI0 6 // Serial Peripheral Interf
-ace 0
=3 #define INTERRUPT_SMBUS0 7 // SMBus0 Interface
=3 #define INTERRUPT_USB0 8 // USB Interface
=3 #define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
=3 #define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
=3 #define INTERRUPT_PCA0 11 // PCA0 Peripheral
=3 #define INTERRUPT_COMPARATOR0 12 // Comparator0
=3 #define INTERRUPT_COMPARATOR1 13 // Comparator1
=3 #define INTERRUPT_TIMER3 14 // Timer3 Overflow
=3 #define INTERRUPT_VBUS_LEVEL 15 // VBUS level-triggered int
-errupt
=3 #define INTERRUPT_UART1 16 // Serial Port 1
=3
=3 //----------------------------------------------------------------
--------------
=3 // Header File PreProcessor Directive
=3 //----------------------------------------------------------------
--------------
=3
=3 #endif // #define C8051F340_H
289 =3
290 =3 //----------------------------------------------------------------
--------------
291 =3 // End Of File
292 =3 //----------------------------------------------------------------
--------------
36 =2 #ifdef DEBUG_TIMEOUTS
37 =2 sbit START_STOP_SPI = P3^0 ;
38 =2 sbit START_STOP_READ_TO = P3^1;
39 =2 sbit START_STOP_WRITE_TO = P3^2;
40 =2
41 =2 #define START_SPI_TIMEOUT (START_STOP_SPI = 1)
42 =2 #define STOP_SPI_TIME_OUT (START_STOP_SPI = 0)
43 =2 #define START_READ_COPY (START_STOP_READ_TO = 1)
44 =2 #define STOP_READ_COPY (START_STOP_READ_TO = 0)
45 =2 #define START_WRITE_COPY (START_STOP_WRITE_TO = 1)
46 =2 #define STOP_WRITE_COPY (START_STOP_WRITE_TO = 0)
47 =2 #else
=2
=2 #define START_SPI_TIMEOUT /\
=2 /
=2 #define STOP_SPI_TIME_OUT /\
=2 /
=2 #define START_READ_COPY /\
=2 /
=2 #define STOP_READ_COPY /\
=2 /
=2 #define START_WRITE_COPY /\
=2 /
=2 #define STOP_WRITE_COPY /\
=2 /
=2
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 16
=2 #endif
63 =2
64 =2 #define ENDLINE "\r\n"
65 =2 #define ENDLINE_SGN '\r'
66 =2
67 =2 #endif
37 =1 // BYTE type definition
38 =1 #ifndef _BYTE_DEF_
39 =1 #define _BYTE_DEF_
40 =1 typedef unsigned char BYTE;
41 =1 #endif /* _BYTE_DEF_ */
42 =1
43 =1 // USB Core Registers
44 =1 #define BASE 0x00
45 =1 #define FADDR BASE
46 =1 #define POWER BASE + 0x01
47 =1 #define IN1INT BASE + 0x02
48 =1 #define OUT1INT BASE + 0x04
49 =1 #define CMINT BASE + 0x06
50 =1 #define IN1IE BASE + 0x07
51 =1 #define OUT1IE BASE + 0x09
52 =1 #define CMIE BASE + 0x0B
53 =1 #define FRAMEL BASE + 0x0C
54 =1 #define FRAMEH BASE + 0x0D
55 =1 #define INDEX BASE + 0x0E
56 =1 #define CLKREC BASE + 0x0F
57 =1 #define E0CSR BASE + 0x11
58 =1 #define EINCSR1 BASE + 0x11
59 =1 #define EINCSR2 BASE + 0x12
60 =1 #define EOUTCSR1 BASE + 0x14
61 =1 #define EOUTCSR2 BASE + 0x15
62 =1 #define E0CNT BASE + 0x16
63 =1 #define EOUTCNTL BASE + 0x16
64 =1 #define EOUTCNTH BASE + 0x17
65 =1 #define FIFO_EP0 BASE + 0x20
66 =1 #define FIFO_EP1 BASE + 0x21
67 =1 #ifdef __F326_VER__
=1 #define FIFO_EP2 BASE + 0x21
=1 #else
70 =1 #define FIFO_EP2 BASE + 0x22
71 =1 #endif
72 =1 #define FIFO_EP3 BASE + 0x23
73 =1
74 =1 // USB Core Register Bits
75 =1
76 =1 // POWER
77 =1 #define rbISOUD 0x80
78 =1 #define rbSPEED 0x40
79 =1 #define rbUSBRST 0x08
80 =1 #define rbRESUME 0x04
81 =1 #define rbSUSMD 0x02
82 =1 #define rbSUSEN 0x01
83 =1
84 =1 // IN1INT
85 =1 #define rbIN3 0x08
86 =1 #define rbIN2 0x04
87 =1 #define rbIN1 0x02
88 =1 #define rbEP0 0x01
89 =1
90 =1 // OUT1INT
91 =1 #define rbOUT3 0x08
92 =1 #ifdef __F326_VER__
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 17
=1 #define rbOUT2 0x02
=1 #else
95 =1 #define rbOUT2 0x04
96 =1 #endif
97 =1 #define rbOUT1 0x02
98 =1
99 =1 // CMINT
100 =1 #define rbSOF 0x08
101 =1 #define rbRSTINT 0x04
102 =1 #define rbRSUINT 0x02
103 =1 #define rbSUSINT 0x01
104 =1
105 =1 // IN1IE
106 =1 #define rbIN3E 0x08
107 =1 #define rbIN2E 0x04
108 =1 #define rbIN1E 0x02
109 =1 #define rbEP0E 0x01
110 =1
111 =1 // OUT1IE
112 =1 #define rbOUT3E 0x08
113 =1 #define rbOUT2E 0x04
114 =1 #define rbOUT1E 0x02
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