📄 f34x_msd_usb_isr.lst
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C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE F34X_MSD_USB_ISR
OBJECT MODULE PLACED IN F34x_MSD_USB_ISR.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\c51.exe F34x_MSD_USB_ISR.c PW(80) SB LC OT(
-9,SIZE) CD DB OE DF(__F340_VER__) LARGE
line level source
1 //----------------------------------------------------------------
--------------
2 // F34x_MSD_USB_ISR.c
3 //----------------------------------------------------------------
--------------
4 // Copyright 2006 Silicon Laboratories, Inc.
5 // http://www.silabs.com
6 //
7 // Program Description:
8 //
9 // Source file for USB firmware. Includes top level isr with Setup
-,
10 // and Endpoint data handlers. Also includes routine for USB susp
-end,
11 // reset, and procedural stall.
12 //
13 // How To Test: See Readme.txt
14 //
15 //
16 // FID: 34X000061
17 // Target: C8051F34x
18 // Tool chain: Keil
19 // Command Line: See Readme.txt
20 // Project Name: F34x_USB_MSD
21 //
22 // Release 1.1
23 // -All changes by PKC
24 // -09 JUN 2006
25 // -Replaced SFR definitions file "c8051f320.h" with "c8051f340
-.h"
26 //
27 // Release 1.0
28 // -Initial Release
29 //
30
31 //----------------------------------------------------------------
--------------
32 // Includes
33 //----------------------------------------------------------------
--------------
34
35 #include "c8051f340.h"
1 =1 //----------------------------------------------------------------
--------------
2 =1 // C8051F340.h
3 =1 //----------------------------------------------------------------
--------------
4 =1 // Copyright 2005 Silicon Laboratories, Inc.
5 =1 // http://www.silabs.com
6 =1 //
7 =1 // Program Description:
8 =1 //
9 =1 // Register/bit definitions for the C8051F34x family.
10 =1 //
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 2
11 =1 //
12 =1 // FID: 34X000002
13 =1 // Target: C8051F340, 'F341, 'F342, 'F343, 'F344, 'F345, '
-F346, 'F347
14 =1 // Tool chain: Keil
15 =1 // Command Line: None
16 =1 //
17 =1 // Release 1.0
18 =1 // -Initial Release (GP\PKC)
19 =1 // -13 DEC 2005
20 =1
21 =1 //----------------------------------------------------------------
--------------
22 =1 // Header File Preprocessor Directive
23 =1 //----------------------------------------------------------------
--------------
24 =1
25 =1 #ifndef C8051F340_H
26 =1 #define C8051F340_H
27 =1
28 =1 //----------------------------------------------------------------
--------------
29 =1 // Byte Registers
30 =1 //----------------------------------------------------------------
--------------
31 =1
32 =1 sfr P0 = 0x80; // Port 0 Latch
33 =1 sfr SP = 0x81; // Stack Pointer
34 =1 sfr DPL = 0x82; // Data Pointer Low
35 =1 sfr DPH = 0x83; // Data Pointer High
36 =1 sfr EMI0TC = 0x84; // EMIF Timing
37 =1 sfr EMI0CF = 0x85; // EMIF Configuration
38 =1 sfr OSCLCN = 0x86; // Internal Low-Freq Oscill
-ator Control
39 =1 sfr PCON = 0x87; // Power Control
40 =1 sfr TCON = 0x88; // Timer/Counter Control
41 =1 sfr TMOD = 0x89; // Timer/Counter Mode
42 =1 sfr TL0 = 0x8A; // Timer/Counter 0 Low
43 =1 sfr TL1 = 0x8B; // Timer/Counter 1 Low
44 =1 sfr TH0 = 0x8C; // Timer/Counter 0 High
45 =1 sfr TH1 = 0x8D; // Timer/Counter 1 High
46 =1 sfr CKCON = 0x8E; // Clock Control
47 =1 sfr PSCTL = 0x8F; // Program Store R/W Contro
-l
48 =1 sfr P1 = 0x90; // Port 1 Latch
49 =1 sfr TMR3CN = 0x91; // Timer/Counter 3Control
50 =1 sfr TMR3RLL = 0x92; // Timer/Counter 3 Reload L
-ow
51 =1 sfr TMR3RLH = 0x93; // Timer/Counter 3 Reload H
-igh
52 =1 sfr TMR3L = 0x94; // Timer/Counter 3Low
53 =1 sfr TMR3H = 0x95; // Timer/Counter 3 High
54 =1 sfr USB0ADR = 0x96; // USB0 Indirect Address Re
-gister
55 =1 sfr USB0DAT = 0x97; // USB0 Data Register
56 =1 sfr SCON0 = 0x98; // UART0 Control
57 =1 sfr SBUF0 = 0x99; // UART0 Data Buffer
58 =1 sfr CPT1CN = 0x9A; // Comparator1 Control
59 =1 sfr CPT0CN = 0x9B; // Comparator0 Control
60 =1 sfr CPT1MD = 0x9C; // Comparator1 Mode Selecti
-on
61 =1 sfr CPT0MD = 0x9D; // Comparator0 Mode Selecti
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 3
-on
62 =1 sfr CPT1MX = 0x9E; // Comparator1 MUX Selectio
-n
63 =1 sfr CPT0MX = 0x9F; // Comparator0 MUX Selectio
-n
64 =1 sfr P2 = 0xA0; // Port 2 Latch
65 =1 sfr SPI0CFG = 0xA1; // SPI Configuration
66 =1 sfr SPI0CKR = 0xA2; // SPI Clock Rate Control
67 =1 sfr SPI0DAT = 0xA3; // SPI Data
68 =1 sfr P0MDOUT = 0xA4; // Port 0 Output Mode Confi
-guration
69 =1 sfr P1MDOUT = 0xA5; // Port 1 Output Mode Confi
-guration
70 =1 sfr P2MDOUT = 0xA6; // Port 2 Output Mode Confi
-guration
71 =1 sfr P3MDOUT = 0xA7; // Port 3 Output Mode Confi
-guration
72 =1 sfr IE = 0xA8; // Interrupt Enable
73 =1 sfr CLKSEL = 0xA9; // Clock Select
74 =1 sfr EMI0CN = 0xAA; // External Memory Interfac
-e Control
75 =1 sfr SBCON1 = 0xAC; // UART1 Baud Rate Generato
-r Control
76 =1 sfr P4MDOUT = 0xAE; // Port 4 Output Mode Confi
-guration
77 =1 sfr PFE0CN = 0xAF; // Prefetch Engine Control
78 =1 sfr P3 = 0xB0; // Port 3 Latch
79 =1 sfr OSCXCN = 0xB1; // External Oscillator Cont
-rol
80 =1 sfr OSCICN = 0xB2; // Internal Oscillator Cont
-rol
81 =1 sfr OSCICL = 0xB3; // Internal Oscillator Cali
-bration
82 =1 sfr SBRLL1 = 0xB4; // UART1 Baud Rate Generato
-r Low
83 =1 sfr SBRLH1 = 0xB5; // UART1 Baud Rate Generato
-r High
84 =1 sfr FLSCL = 0xB6; // Flash Scale
85 =1 sfr FLKEY = 0xB7; // Flash Lock and Key
86 =1 sfr IP = 0xB8; // Interrupt Priority
87 =1 sfr CLKMUL = 0xB9; // Clock Multiplier
88 =1 sfr AMX0N = 0xBA; // AMUX0 Negative Channel S
-elect
89 =1 sfr AMX0P = 0xBB; // AMUX0 Positive Channel S
-elect
90 =1 sfr ADC0CF = 0xBC; // ADC0 Configuration
91 =1 sfr ADC0L = 0xBD; // ADC0 Low
92 =1 sfr ADC0H = 0xBE; // ADC0 High
93 =1 sfr SMB0CN = 0xC0; // SMBus Control
94 =1 sfr SMB0CF = 0xC1; // SMBus Configuration
95 =1 sfr SMB0DAT = 0xC2; // SMBus Data
96 =1 sfr ADC0GTL = 0xC3; // ADC0 Greater-Than Compar
-e Low
97 =1 sfr ADC0GTH = 0xC4; // ADC0 Greater-Than Compar
-e High
98 =1 sfr ADC0LTL = 0xC5; // ADC0 Less-Than Compare W
-ord Low
99 =1 sfr ADC0LTH = 0xC6; // ADC0 Less-Than Compare W
-ord High
100 =1 sfr P4 = 0xC7; // Port 4 Latch
101 =1 sfr TMR2CN = 0xC8; // Timer/Counter 2 Control
102 =1 sfr REG0CN = 0xC9; // Voltage Regulator Contro
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 4
-l
103 =1 sfr TMR2RLL = 0xCA; // Timer/Counter 2 Reload L
-ow
104 =1 sfr TMR2RLH = 0xCB; // Timer/Counter 2 Reload H
-igh
105 =1 sfr TMR2L = 0xCC; // Timer/Counter 2 Low
106 =1 sfr TMR2H = 0xCD; // Timer/Counter 2 High
107 =1 sfr PSW = 0xD0; // Program Status Word
108 =1 sfr REF0CN = 0xD1; // Voltage Reference Contro
-l
109 =1 sfr SCON1 = 0xD2; // UART1 Control
110 =1 sfr SBUF1 = 0xD3; // UART1 Data Buffer
111 =1 sfr P0SKIP = 0xD4; // Port 0 Skip
112 =1 sfr P1SKIP = 0xD5; // Port 1 Skip
113 =1 sfr P2SKIP = 0xD6; // Port 2 Skip
114 =1 sfr USB0XCN = 0xD7; // USB0 Transceiver Control
115 =1 sfr PCA0CN = 0xD8; // PCA0 Control
116 =1 sfr PCA0MD = 0xD9; // PCA0 Mode
117 =1 sfr PCA0CPM0 = 0xDA; // PCA0 Module 0 Mode Regis
-ter
118 =1 sfr PCA0CPM1 = 0xDB; // PCA0 Module 1 Mode Regis
-ter
119 =1 sfr PCA0CPM2 = 0xDC; // PCA0 Module 2 Mode Regis
-ter
120 =1 sfr PCA0CPM3 = 0xDD; // PCA0 Module 3 Mode Regis
-ter
121 =1 sfr PCA0CPM4 = 0xDE; // PCA0 Module 4 Mode Regis
-ter
122 =1 sfr P3SKIP = 0xDF; // Port 3 Skip
123 =1 sfr ACC = 0xE0; // Accumulator
124 =1 sfr XBR0 = 0xE1; // Port I/O Crossbar Contro
-l 0
125 =1 sfr XBR1 = 0xE2; // Port I/O Crossbar Contro
-l 1
126 =1 sfr XBR2 = 0xE3; // Port I/O Crossbar Contro
-l 2
127 =1 sfr IT01CF = 0xE4; // INT0/INT1 Configuration
128 =1 sfr SMOD1 = 0xE5; // UART1 Mode
129 =1 sfr EIE1 = 0xE6; // Extended Interrupt Enabl
-e 1
130 =1 sfr EIE2 = 0xE7; // Extended Interrupt Enabl
-e 2
131 =1 sfr ADC0CN = 0xE8; // ADC0 Control
132 =1 sfr PCA0CPL1 = 0xE9; // PCA0 Capture 1 Low
133 =1 sfr PCA0CPH1 = 0xEA; // PCA0 Capture 1 High
134 =1 sfr PCA0CPL2 = 0xEB; // PCA0 Capture 2 Low
135 =1 sfr PCA0CPH2 = 0xEC; // PCA0 Capture 2 High
136 =1 sfr PCA0CPL3 = 0xED; // PCA0 Capture 3 Low
137 =1 sfr PCA0CPH3 = 0xEE; // PCA0 Capture 3 High
138 =1 sfr RSTSRC = 0xEF; // Reset Source Configurati
-on/Status
139 =1 sfr B = 0xF0; // B Register
140 =1 sfr P0MDIN = 0xF1; // Port 0 Input Mode Config
-uration
141 =1 sfr P1MDIN = 0xF2; // Port 1 Input Mode Config
-uration
142 =1 sfr P2MDIN = 0xF3; // Port 2 Input Mode Config
-uration
143 =1 sfr P3MDIN = 0xF4; // Port 3 Input Mode Config
-uration
144 =1 sfr P4MDIN = 0xF5; // Port 4 Input Mode Config
-uration
C51 COMPILER V7.50 F34X_MSD_USB_ISR 11/28/2006 10:54:34 PAGE 5
145 =1 sfr EIP1 = 0xF6; // Extended Interrupt Prior
-ity 1
146 =1 sfr EIP2 = 0xF7; // Extended Interrupt Prior
-ity 2
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