fads.h

Linux2.4.27在AT91RM9200下的U-BOOT代码。可以在Redhat9等版本下使用。适合ARM学习者使用。

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
 * and Dan Malek
 *
 * Modified by, Yuli Barcohen, Arabella Software Ltd., [e-mail]
 *
 * This header file contains values common to all FADS family boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/****************************************************************************
 * Flash Memory Map as used by U-Boot:
 *
 *                          Start Address    Length
 * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
 * |                       | 0xFE00_0100     Reset Vector
 * +                       + 0xFE0?_????
 * | U-Boot code           |
 * |                       |
 * +-----------------------+ 0xFE04_0000 (sector border)
 * |                       |
 * |                       |
 * | U-Boot environment    |
 * |                       |                                 ^
 * |                       |                                 | U-Boot
 * +=======================+ 0xFE08_0000 (sector border)    -----------------
 * | Available             |                                 | Applications
 * | ...                   |                                 v
 *
 *****************************************************************************/
/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
/* in general, we always know this for FADS+new ADS anyway */
#define CONFIG_8xx_GCLK_FREQ     ((CFG_8XX_XIN) * (CFG_8XX_FACT))

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
    "dhcp;"									\
    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "		\
    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\
    "bootm"

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * New MPC86xADS and Duet provide two Ethernet connectivity options:
 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
 * got FEC so FEC is the default.
 */
#ifndef CONFIG_ADS
#undef	CONFIG_SCC1_ENET		/* Disable SCC1 ethernet */
#define	CONFIG_FEC_ENET			/* Use FEC ethernet  */
#else					/* Old ADS has not got FEC option */
#define	CONFIG_SCC1_ENET		/* Use SCC1 ethernet */
#undef	CONFIG_FEC_ENET			/* No FEC ethernet  */
#endif /* !CONFIG_ADS */

#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#ifdef CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#endif

#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS	(CONFIG_CMD_DFL  \
			 | CFG_CMD_DHCP  \
			 | CFG_CMD_IMMAP \
			 | CFG_CMD_MII   \
			 | CFG_CMD_PING  \
			)
#endif /* !CONFIG_COMMANDS */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#undef	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_LOAD_ADDR	 	0x00100000

#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */
#define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
#elif defined(CONFIG_FADS)				/* Old/new FADS */
#define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
#else							/* Old ADS */
#define	CFG_SDRAM_SIZE		0x00000000		/* No SDRAM */
#endif

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#if (CFG_SDRAM_SIZE)
#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
#else
#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
#endif /* CFG_SDRAM_SIZE */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * Flash organization
 */
#define CFG_FLASH_BASE		TEXT_BASE
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
#define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/

#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * I2C configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE		0x7F
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */