dsp.c

Linux2.4.27在AT91RM9200下的U-BOOT代码。可以在Redhat9等版本下使用。适合ARM学习者使用。

/*
 * Intracom TI6711 DSP
 */

#include <common.h>
#include <post.h>

#include "mpc8xx.h"

struct ram_range {
	u32 start;
	u32 size;
};

static const struct ram_range int_ram[] = {
	{ 0x00000000U, 0x00010000U },
};

static const struct ram_range ext_ram[] = {
	{ 0x80000000U, 0x00100000U },
};

static const struct ram_range ranges[] = {
	{ 0x00000000U, 0x00010000U },
	{ 0x80000000U, 0x00100000U },
};

/*******************************************************************************************************/

static inline int addr_in_int_ram(u32 addr)
{
	int i;

	for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
		if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
			return 1;

	return 0;
}

static inline int addr_in_ext_ram(u32 addr)
{
	int i;

	for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
		if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
			return 1;

	return 0;
}

/*******************************************************************************************************/

#define DSP_HPIC	0x0
#define DSP_HPIA	0x4
#define DSP_HPID1	0x8
#define DSP_HPID2	0xC

static u32 dummy_delay;
static volatile u32 *ti6711_delay = &dummy_delay;

static inline void dsp_go_slow(void)
{
	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;

	memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
	memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;

	ti6711_delay = (u32 *)DUMMY_BASE;
}

static inline void dsp_go_fast(void)
{
	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;

	memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
	memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;

	ti6711_delay = &dummy_delay;
}

/*******************************************************************************************************/

static inline void dsp_delay(void)
{
	/* perform ti6711_delay chip select read to have a small delay */
	(void) *(volatile u32 *)ti6711_delay;
}

static inline u16 dsp_read_hpic(void)
{
	return *((volatile u16 *)DSP_BASE);
}

static inline void dsp_write_hpic(u16 val)
{
	*((volatile u16 *)DSP_BASE) = val;
}

static inline void dsp_reset(void)
{
	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
	udelay(250);
	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
	udelay(250);
}

static inline void dsp_init_hpic(void)
{
	int i;
	volatile u16 *p;

	dsp_go_slow();

	i = 0;
	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
		dsp_delay();
		i++;
	}
	dsp_delay();

	/* write control register */
	p = (volatile u16 *)DSP_BASE;
	p[0] = 0x0000;
	dsp_delay();
	p[1] = 0x0000;
	dsp_delay();

	dsp_go_fast();
}

static inline void dsp_wait_hrdy(void)
{
	int i;

	i = 0;
	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
		dsp_delay();
		i++;
	}
}

static inline u32 dsp_read_hpic_word(u32 addr)
{
	u32 val;
	volatile u16 *p;

	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);

	val = ((u32) p[0] << 16);
	dsp_delay();

	val |= p[1];
	dsp_delay();

	return val;
}

static inline u16 dsp_read_hpic_hi_hword(u32 addr)
{
	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
}

static inline u16 dsp_read_hpic_lo_hword(u32 addr)
{
	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
}

static inline void dsp_write_hpic_word(u32 addr, u32 val)
{
	volatile u16 *p;

	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
	p[0] = (u16)(val >> 16);
	dsp_delay();

	p[1] = (u16)val;
	dsp_delay();
}

static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
{
	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
}

static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
{
	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
}

/********************************************************************/

static inline void c62_write_word(u32 addr, u32 val)
{
	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
	dsp_delay();
	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
	dsp_delay();

	dsp_wait_hrdy();
	dsp_delay();

	dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
	dsp_delay();

	dsp_wait_hrdy();
	dsp_delay();

	dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
	dsp_delay();
}

static u32 c62_read_word(u32 addr)
{
	u32 val;

	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
	dsp_delay();
	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
	dsp_delay();

	/* FETCH */
	dsp_write_hpic(0x10);
	dsp_delay();

	dsp_wait_hrdy();
	dsp_delay();

	val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
	dsp_delay();

	dsp_wait_hrdy();
	dsp_delay();

	val |= dsp_read_hpic_lo_hword(DSP_HPID2);
	dsp_delay();

	return val;
}

static inline void c62_read(u32 addr, u32 *buffer, int numdata)
{
	int i;

	if (numdata <= 0)
		return;

	for (i = 0; i < numdata; i++) {
		*buffer++ = c62_read_word(addr);
		addr += 4;
	}
}

static inline u32 c62_checksum(u32 addr, int numdata)
{
	int i;
	u32 chksum;

	chksum = 0;
	for (i = 0; i < numdata; i++) {
		chksum += c62_read_word(addr);
		addr += 4;
	}

	return chksum;
}

static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
{
	int i;

	if (numdata <= 0)
		return;

	for (i = 0; i < numdata; i++) {
		c62_write_word(addr, *buffer++);
		addr += 4;
	}
}

static inline int c62_write_word_validated(u32 addr, u32 val)
{
	c62_write_word(addr, val);
	return c62_read_word(addr) == val ? 0 : -1;
}

static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
{
	int i, r;

	if (numdata <= 0)
		return 0;

	for (i = 0; i < numdata; i++) {
		r = c62_write_word_validated(addr, *buffer++);
		if (r < 0)
			return r;
		addr += 4;
	}
	return 0;
}

/***********************************************************************************************************/

static const u8 bootstrap_rbin[5084] = {
	0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
	0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
	0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,