memsetup.s

Linux2.4.27在AT91RM9200下的U-BOOT代码。可以在Redhat9等版本下使用。适合ARM学习者使用。

/*
 * (C) Copyright 2004
 * METER Chen
 *
 * http://www.cmtekchina.com
 * mailto:[e-mail]
 *
 * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
 * Modified By MATTO
 *
 * Copyright (C) 2001 Erik Mouw ([e-mail])
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

/*
 * Documentation:
 * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
 *     Advanced Developer's manual, December 1999
 *
 * Intel has a very hard to find SDRAM configurator on their web site:
 *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
 *
 * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
 * appears to be true, but it might be possible that somebody designs a
 * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
 *
 * 04-10-2001:  SELETZ
 * - separated memory config for multiple platform support
 * - perform SA1110 Hardware Reset Procedure
 *
 */

.equ	fMCLK,		50000000	/* 50MHz, KS32C50100 */

/* -> EXTDBWTH : Memory Bus Width register */

/* 0-disable, 1-byte, 2-halfword, 3-word */
.equ	DSR0,		(2<<0)	/* ROM0 */		
.equ	DSR1,		(2<<2)	/* ROM1 */
.equ	DSR2,		(1<<4)  /* ROM2 */
.equ	DSR3,		(3<<6)	/* ROM3 */
.equ	DSR4,		(3<<8)	/* ROM4 */
.equ	DSR5,		(3<<10)	/* ROM5	*/
.equ	DSD0,		(3<<12)	/* DRAM0 */
.equ	DSD1,		(3<<14)	/* DRAM1 */
.equ	DSD2,		(3<<16)	/* DRAM2 */
.equ	DSD3,		(3<<18) /* DRAM3 */	
.equ	DSX0,		(1<<20)	/* EXTIO0 */
.equ	DSX1,		(1<<22)	/* EXTIO1 */
.equ	DSX2,		(1<<24)	/* EXTIO2 */
.equ	DSX3,		(1<<26)	/* EXTIO3 */

.equ	rEXTDBWTH,	(DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)


/* -> ROMCON0 : ROM Bank0 Control register */
.equ	ROMBasePtr0,	(0x000<<10)	/* =0x0000000 */  
.equ	ROMEndPtr0,	(0x020<<20)	/* =0x0200000 */

/* REMAP */  
.equ	ROMBasePtr0_S,	(0x100<<10)	/* =0x1000000 */ 
.equ	ROMEndPtr0_S,	(0x120<<20)	/* =0x1200000 */  

.equ	PMC0,		(0x0)		/* 0x0=Normal ROM, 0x1=4Word Page */ 
                                	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa0,		(0x0<<2)	/* 0x0=5Cycle, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
.equ	rTacc0,		(0x6<<4)	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                    	/* 0x4=5Cycle, 0x5=6Cycle */
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON0,	(ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0)
.equ	rROMCON0_S,	(ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)

/* -> ROMCON1 : ROM Bank1 Control register */
.equ	ROMBasePtr1,	(0x020<<10)	/* =0x0200000 */  
.equ	ROMEndPtr1,	(0x040<<20)   	/* =0x0400000 */  

.equ	ROMBasePtr1_S,	(0x120<<10)	/* =0x1200000 */  
.equ	ROMEndPtr1_S,   (0x140<<20)   	/* =0x1400000 */  
.equ	PMC1,          	(0x0)           /* 0x0=Normal ROM, 0x1=4Word Page */ 
                                    	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa1,         	(0x0<<2)    	/* 0x0=5Cycle, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */ 
.equ 	rTacc1,		(0x4<<4)	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                    	/* 0x4=5Cycle, 0x5=6Cycle */
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON1,   	(ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1)
.equ	rROMCON1_S, 	(ROMEndPtr1_S+ROMBasePtr1_S+rTacc1+rTpa1+PMC1)

/* -> ROMCON2 : ROM Bank2 Control register */
.equ	ROMBasePtr2,	(0x040<<10)	/* =0x0400000 */  
.equ	ROMEndPtr2,      (0x060<<20)  	/* =0x0600000 */  

.equ	ROMBasePtr2_S,	(0x140<<10)	/* =0x1400000 */  
.equ	ROMEndPtr2_S, 	(0x160<<20)	/* =0x1600000 */  

.equ	PMC2,          	(0x0)		/* 0x0=Normal ROM, 0x1=4Word Page */ 
                                    	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa2,         	(0x0<<2)	/* 0x0=5Cycle, 0x1=2Cycle */
                                   	/* 0x2=3Cycle, 0x3=4Cycle */ 
.equ	rTacc2,        	(0x6<<4)	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                   	/* 0x4=5Cycle, 0x5=6Cycle */
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON2,   	(ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2)
.equ	rROMCON2_S, 	(ROMEndPtr2_S+ROMBasePtr2_S+rTacc2+rTpa2+PMC2)

/* -> ROMCON3 : ROM Bank3 Control register */
.equ	ROMBasePtr3, 	(0x060<<10)	/* =0x0600000 */  
.equ	ROMEndPtr3,    	(0x080<<20)   	/* =0x0800000 */ 

.equ	ROMBasePtr3_S, 	(0x060<<10)	/* =0x1600000 */  
.equ	ROMEndPtr3_S,  	(0x080<<20)	/* =0x1800000 */  
.equ	PMC3,          	(0x0)		/* 0x0=Normal ROM, 0x1=4Word Page */ 
                                    	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa3,         	(0x0<<2)	/* 0x0=5Cycle, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
.equ	rTacc3, 	(0x6<<4)    	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                    	/* 0x4=5Cycle, 0x5=6Cycle */
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON3, 	(ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3)
.equ	rROMCON3_S, 	(ROMEndPtr3_S+ROMBasePtr3_S+rTacc3+rTpa3+PMC3)

/* -> ROMCON4 : ROM Bank4 Control register */
.equ	ROMBasePtr4,  	(0x080<<10)  	/* =0x0800000 */ 
.equ	ROMEndPtr4,     (0x0A0<<20)	/* =0x0A00000 */  

.equ	ROMBasePtr4_S, 	(0x180<<10)	/* =0x1800000 */  
.equ	ROMEndPtr4_S,  	(0x1A0<<20)	/* =0x1A00000 */  
.equ	PMC4,          	(0x0)		/* 0x0=Normal ROM, 0x1=4Word Page */ 
                                    	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa4,         	(0x0<<2)  	/* 0x0=5Cycle, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
.equ	rTacc4,       	(0x4<<4)	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                    	/* 0x4=5Cycle, 0x5=6Cycle */ 
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON4,   	(ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4)
.equ	rROMCON4_S,	(ROMEndPtr4_S+ROMBasePtr4_S+rTacc4+rTpa4+PMC4)

/* -> ROMCON5 : ROM Bank5 Control register */
.equ	ROMBasePtr5, 	(0x0A0<<10)	/* =0x0A00000 */ 
.equ	ROMEndPtr5,    	(0x0C0<<20)	/* =0x0C00000 */  

.equ	ROMBasePtr5_S, 	(0x1A0<<10)	/* =0x1A00000 */  
.equ	ROMEndPtr5_S,  	(0x1C0<<20)	/* =0x1C00000 */  

.equ	PMC5,      	(0x0)		/* 0x0=Normal ROM, 0x1=4Word Page */ 
                                    	/* 0x2=8Word Page, 0x3=16Word Page */
.equ	rTpa5,         	(0x0<<2) 	/* 0x0=5Cycle, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
.equ	rTacc5,        	(0x4<<4)   	/* 0x0=Disable, 0x1=2Cycle */
                                    	/* 0x2=3Cycle, 0x3=4Cycle */
                                    	/* 0x4=5Cycle, 0x5=6Cycle */
                                    	/* 0x6=7Cycle, 0x7=Reserved */
.equ	rROMCON5,  	(ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5)
.equ	rROMCON5_S, 	(ROMEndPtr5_S+ROMBasePtr5_S+rTacc5+rTpa5+PMC5)

/* -> DRAMCON0 : RAM Bank0 control register */
.equ	SRAS2CASDelay0,		1                   	/* (Trc)0=1cycle,1=2cycle */
.equ	SRASPrechargeTime0,	3			/* (Trp)0=1cycle ~ 3=4clcyle */
.equ	SNoColumnAddr0,		0                      	/* 0=8bit,1=9bit,2=10bit,3=11bits */
.equ	SCAN0,              	(SNoColumnAddr0<<30)
.equ	STrc0,               	(SRAS2CASDelay0<<7)
.equ	STrp0,               	(SRASPrechargeTime0<<8)

.equ	DRAMBasePtr0,  		(0x100<<10)           	/* =0x1000000 */  
.equ	DRAMEndPtr0,        	(0x200<<20)           	/* =0x2000000 */ 

.equ	DRAMBasePtr0_S,     	(0x000<<10)           	/* =0x0000000 */  
.equ	DRAMEndPtr0_S,      	(0x040<<20)           	/* =0x0200000 */ 

.equ	rSDRAMCON0,	 	(SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0)
.equ	rSDRAMCON0_S,    	(SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0)

/* -> DRAMCON1 : RAM Bank1 control register */
.equ	SRAS2CASDelay1,		1                     	/* (Trc)0=1cycle,1=2cycle */
.equ	SRASPrechargeTime1,  	1 	                /* (Trp)0=1cycle ~ 3=4clcyle */
.equ	SNoColumnAddr1,      	0       	        /* 0=8bit,1=9bit,2=10bit,3=11bits */
.equ	SCAN1,			(SNoColumnAddr1<<30)
.equ	STrc1,			(SRAS2CASDelay1<<7)
.equ	STrp1,              	(SRASPrechargeTime1<<8)

.equ	DRAMBasePtr1,   	(0x200<<10)		/* =0x12000000 */  
.equ	DRAMEndPtr1,        	(0x220<<20)           	/* =0x14000000 */ 

.equ	DRAMBasePtr1_S,     	(0x040<<10)          	/* =0x04000000 */  
.equ	DRAMEndPtr1_S,   	(0x080<<20)         	/* =0x08000000 */ 

.equ	rSDRAMCON1,		(SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1)  		
.equ	rSDRAMCON1_S,		(SCAN1+DRAMEndPtr1_S+DRAMBasePtr1_S+STrp1+STrc1)  		

/* -> DRAMCON2 : RAM Bank2 control register */
.equ	SRAS2CASDelay2,      	1                   	/* (Trc)0=1cycle,1=2cycle */
.equ	SRASPrechargeTime2,	1                      	/* (Trp)0=1cycle ~ 3=4clcyle */
.equ	SNoColumnAddr2,      	0                      	/* 0=8bit,1=9bit,2=10bit,3=11bits */
.equ	SCAN2,               	(SNoColumnAddr2<<30)
.equ	STrc2,               	(SRAS2CASDelay2<<7)
.equ	STrp2,               	(SRASPrechargeTime2<<8)

.equ	DRAMBasePtr2,  		(0x220<<10)        	/* =0x14000000 */  
.equ	DRAMEndPtr2,        	(0x240<<20)           	/* =0x18000000 */ 

.equ	DRAMBasePtr2_S,     	(0x080<<10)           	/* =0x08000000 */  
.equ	DRAMEndPtr2_S,      	(0x0C0<<20)           	/* =0x0C000000 */

.equ	rSDRAMCON2,		(SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2)  		
.equ	rSDRAMCON2_S,		(SCAN2+DRAMEndPtr2_S+DRAMBasePtr2_S+STrp2+STrc2)  		

/* -> DRAMCON3 : RAM Bank3 control register */
.equ	SRAS2CASDelay3,      	1                     	/* (Trc)0=1cycle,1=2cycle */
.equ	SRASPrechargeTime3,  	1                      	/* (Trp)0=1cycle ~ 3=4clcyle */
.equ	SNoColumnAddr3,      	0                      	/* 0=8bit,1=9bit,2=10bit,3=11bits */
.equ	SCAN3,               	(SNoColumnAddr3<<30)
.equ	STrc3,               	(SRAS2CASDelay3<<7)
.equ	STrp3,               	(SRASPrechargeTime3<<8)

.equ	DRAMBasePtr3,  		(0x240<<10)          	/* =0x14000000 */  
.equ	DRAMEndPtr3,        	(0x260<<20)           	/* =0x18000000 */ 

.equ	DRAMBasePtr3_S,     	(0x0C0<<10)           	/* =0x0C000000 */  
.equ	DRAMEndPtr3_S,      	(0x100<<20)           	/* =0x10000000 */
 
.equ	rSDRAMCON3,		(SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3)  		
.equ	rSDRAMCON3_S,		(SCAN3+DRAMEndPtr3_S+DRAMBasePtr3_S+STrp3+STrc3)  		

;/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
.equ	RefCycle,     		16 			/* Unit [us], 1k refresh 16ms */
.equ	CASSetupTime,    	0    			/* 0=1cycle, 1=2cycle */
.equ	CASHoldTime,     	0	    		/* 0=1cycle, 1=2cycle, 2=3cycle */
                           				/* 3=4cycle, 4=5cycle */
.equ	RefCycleValue,   	((2048+1-(RefCycle*fMCLK))<<21)
.equ	Tcsr,            	(CASSetupTime<<20)  	/* 1cycle */
.equ	Tcs,             	(CASHoldTime<<17)    
.equ	ExtIOBase,       	0x18360		      	/* Refresh enable, VSF=1 */

.equ	rREFEXTCON,      	(RefCycleValue+Tcsr+Tcs+ExtIOBase)
/*.equ	SRefCycle,       	16*/   			/* Unit [us], 4k refresh 64ms */
.equ	SRefCycle,     		8   			/* Unit [us], 4k refresh 64ms */
.equ	ROWcycleTime,    	3    			/* 0=1cycle, 1=2cycle, 2=3cycle */
                           				/* 3=4cycle, 4=5cycle */
.equ	SRefCycleValue,  	((2048+1-(SRefCycle*fMCLK))<<21)
.equ	STrc,            	(ROWcycleTime<<17)    
.equ	rSREFEXTCON,     	(SRefCycleValue+STrc+ExtIOBase)


MEMORY_CONFIG:
	.long	rEXTDBWTH	/* DRAM1(Half), ROM5(Byte), ROM1(Half), else 32bit */
	.long	rROMCON0	/* 0x0000000 ~ 0x01FFFFF, ROM0,2MByte,2cycle */
	.long	rROMCON1	 
    	.long	rROMCON2	/* 0x0400000 ~ 0x05FFFFF, ROM2 */
	.long	rROMCON3	/* 0x0600000 ~ 0x07FFFFF, ROM3 */
	.long	rROMCON4	/* 0x0800000 ~ 0x09FFFFF, ROM4 */
	.long	rROMCON5	 
	.long	rSDRAMCON0  	/* 0x1000000 ~ 0x1FFFFFF, DRAM0 16M */
	.long	rSDRAMCON1	/* 0x1400000 ~ 0x17FFFFF, DRAM1 4M */
	.long	rSDRAMCON2	/* 0x1800000 ~ 0x1EFFFFF, DRAM2 16M */
	.long	rSDRAMCON3	/*  0x1C00000 ~ 0x1FFFFFF */
	.long	rSREFEXTCON 	/* External I/O, Refresh */	

.globl memsetup
memsetup:
	LDR	r0, =0x3FF0000		 
	LDR	r1, =0x83FFFF90	/*SetValue = 0x83FFFF91*/
	STR	r1, [r0]	/*Cache,WB disable*/
                           	/*Start_addr = 0x3FF00000*/
	
	/* use pc relative address */
	adr r0, MEMORY_CONFIG	

	ldmia r0, {r1-r12}
	ldr   r0,  =(0x3FF0000 + 0x3010)
	stmia r0, {r1-r12}
	mov pc, lr