mct_u232.h

基于S3CEB2410平台LINUX操作系统下 USB驱动源代码

 *  bRequest:       0xa
 *  wValue:         0x0
 *  wIndex:         0x0
 *  wLength:        0x1
 *  Data:           MCR (Bit 4..7, see below)
 *
 *  Bit 7: Reserved, always 0.
 *  Bit 6: Reserved, always 0.
 *  Bit 5: Reserved, always 0.
 *  Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver
 *  	   are internally connected together to allow diagnostic operations. In
 *  	   addition, the UART modem control outputs are connected to the UART
 *  	   modem control inputs. CTS is connected to RTS, DTR is connected to
 *  	   DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD.
 *  Bit 3: OUT 2. An auxiliary output that the host processor may set high or
 *  	   low. In the IBM PC serial adapter (and most clones), OUT 2 is used
 *  	   to tri-state (disable) the interrupt signal from the
 *  	   8250/16450/16550 UART.
 *  Bit 2: OUT 1. An auxiliary output that the host processor may set high or
 *  	   low. This output is not used on the IBM PC serial adapter.
 *  Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS
 *  	   line is Low (Active).
 *  Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART
 *  	   -DTR line is Low (Active).
 *
 *  SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been
 *  seen _always_ set.
 *
 *
 * Modem Status Register (MSR)
 * ---------------------------
 *
 *  BmRequestType:  0xc  (1100 0000B)
 *  bRequest:       0x2
 *  wValue:         0x0
 *  wIndex:         0x0
 *  wLength:        0x1
 *  Data:           MSR (see below)
 *
 *  Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the
 *  	   UART.
 *  Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART.
 *  Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART.
 *  Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART.
 *  Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has
 *  	   changed state one more more times since the last time the MSR was
 *  	   read by the host.
 *  Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has
 *  	   had a low to high transition since the last time the MSR was read by
 *  	   the host.
 *  Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed
 *  	   state one more more times since the last time the MSR was read by the
 *  	   host.
 *  Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed
 *  	   state one more times since the last time the MSR was read by the
 *  	   host.
 *
 *  SniffUSB observations: the MSR is also returned as first byte on the
 *  interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB
 *  request to read MSR cannot be applied during normal device operation.
 *
 *
 * Line Status Register (LSR)
 * --------------------------
 *
 *  Bit 7   Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
 *  	    This bit is set to "1" when any of the bytes in the FIFO have one or
 *  	    more of the following error conditions: PE, FE, or BI.
 *  Bit 6   Transmitter Empty (TEMT). When set to "1", there are no words
 *  	    remaining in the transmit FIFO or the transmit shift register. The
 *  	    transmitter is completely idle.
 *  Bit 5   Transmitter Holding Register Empty (THRE). When set to "1", the FIFO
 *  	    (or holding register) now has room for at least one additional word
 *  	    to transmit. The transmitter may still be transmitting when this bit
 *  	    is set to "1".
 *  Bit 4   Break Interrupt (BI). The receiver has detected a Break signal.
 *  Bit 3   Framing Error (FE). A Start Bit was detected but the Stop Bit did not
 *  	    appear at the expected time. The received word is probably garbled.
 *  Bit 2   Parity Error (PE). The parity bit was incorrect for the word received.
 *  Bit 1   Overrun Error (OE). A new word was received and there was no room in
 *  	    the receive buffer. The newly-arrived word in the shift register is
 *  	    discarded. On 8250/16450 UARTs, the word in the holding register is
 *  	    discarded and the newly- arrived word is put in the holding register.
 *  Bit 0   Data Ready (DR). One or more words are in the receive FIFO that the
 *  	    host may read. A word must be completely received and moved from the
 *  	    shift register into the FIFO (or holding register for 8250/16450
 *  	    designs) before this bit is set.
 *
 *  SniffUSB observations: the LSR is returned as second byte on the interrupt-in
 *  endpoint 0x83 to signal error conditions. Such errors have been seen with
 *  minicom/zmodem transfers (CRC errors).
 *
 *
 * Flow control
 * ------------
 *
 *  SniffUSB observations: no flow control specific requests have been realized
 *  apart from DTR/RTS settings. Both signals are dropped for no flow control
 *  but asserted for hardware or software flow control.
 *
 *
 * Endpoint usage
 * --------------
 *
 *  SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint
 *  0x81 is used to transmit and receive characters. The second interrupt-in 
 *  endpoint 0x83 signals exceptional conditions like modem line changes and 
 *  errors. The first byte returned is the MSR and the second byte the LSR.
 *
 *
 * Other observations
 * ------------------
 *
 *  Queued bulk transfers like used in visor.c did not work. 
 *  
 *
 * Properties of the USB device used (as found in /var/log/messages)
 * -----------------------------------------------------------------
 *
 *  Manufacturer: MCT Corporation.
 *  Product: USB-232 Interfact Controller
 *  SerialNumber: U2S22050
 *
 *    Length              = 18
 *    DescriptorType      = 01
 *    USB version         = 1.00
 *    Vendor:Product      = 0711:0210
 *    MaxPacketSize0      = 8
 *    NumConfigurations   = 1
 *    Device version      = 1.02
 *    Device Class:SubClass:Protocol = 00:00:00
 *      Per-interface classes
 *  Configuration:
 *    bLength             =    9
 *    bDescriptorType     =   02
 *    wTotalLength        = 0027
 *    bNumInterfaces      =   01
 *    bConfigurationValue =   01
 *    iConfiguration      =   00
 *    bmAttributes        =   c0
 *    MaxPower            =  100mA
 *
 *    Interface: 0
 *    Alternate Setting:  0
 *      bLength             =    9
 *      bDescriptorType     =   04
 *      bInterfaceNumber    =   00
 *      bAlternateSetting   =   00
 *      bNumEndpoints       =   03
 *      bInterface Class:SubClass:Protocol =   00:00:00
 *      iInterface          =   00
 *      Endpoint:
 * 	  bLength             =    7
 * 	  bDescriptorType     =   05
 * 	  bEndpointAddress    =   81 (in)
 * 	  bmAttributes        =   03 (Interrupt)
 * 	  wMaxPacketSize      = 0040
 * 	  bInterval           =   02
 *      Endpoint:
 * 	  bLength             =    7
 * 	  bDescriptorType     =   05
 * 	  bEndpointAddress    =   01 (out)
 * 	  bmAttributes        =   02 (Bulk)
 * 	  wMaxPacketSize      = 0040
 * 	  bInterval           =   00
 *      Endpoint:
 * 	  bLength             =    7
 * 	  bDescriptorType     =   05
 * 	  bEndpointAddress    =   83 (in)
 * 	  bmAttributes        =   03 (Interrupt)
 * 	  wMaxPacketSize      = 0002
 * 	  bInterval           =   02
 *
 *
 * Hardware details (added by Martin Hamilton, 2001/12/06)
 * -----------------------------------------------------------------
 *
 * This info was gleaned from opening a Belkin F5U109 DB9 USB serial
 * adaptor, which turns out to simply be a re-badged U232-P9.  We
 * know this because there is a sticky label on the circuit board
 * which says "U232-P9" ;-)
 * 
 * The circuit board inside the adaptor contains a Philips PDIUSBD12
 * USB endpoint chip and a Phillips P87C52UBAA microcontroller with
 * embedded UART.  Exhaustive documentation for these is available at:
 *
 *   http://www.semiconductors.philips.com/pip/p87c52ubaa
 *   http://www.semiconductors.philips.com/pip/pdiusbd12
 *
 * Thanks to Julian Highfield for the pointer to the Philips database.
 * 
 */

#endif /* __LINUX_USB_SERIAL_MCT_U232_H */