s2pctrl.vhd

罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, PhD提供的示波器开发全文挡及C,VHDL代码.

-- 's2pctrl' is the control part of the acquisition module
-- it implements the communication protocol with the A/D converter
-- sends control signals to the A/D (convst, sclk)
-- retrieves data (din)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity s2pctrl is
  port (rst     : in std_logic;
        mclk    : in std_logic;
        sample  : in std_logic; -- tells it's ok to start a conversion
        convst  : out std_logic; -- start the conversion
        sclk    : out std_logic;
        load    : out std_logic;
        sh_en   : out std_logic;
        rdy     : out std_logic); -- the conversion is ready
end s2pctrl;

architecture Behavioral of s2pctrl is

signal cnt: std_logic_vector(7 downto 0) := (others => '0');

begin

-- with the help of 'cnt' the controller obeys the timing of the A/D converter signals 
process(mclk, sample,cnt)
begin

  if (sample = '1') then
    cnt <= (others => '0'); -- it's ok to start
  elsif (mclk'event and mclk = '1') then
    cnt <= cnt + 1;
  end if;

  if (cnt = X"FF") then
    cnt(0) <= '0'; -- prevents the counter to overflow (keeps it at X"FE")starting a conversion without the consent of osc_ctrl 
                   -- ('cnt' should be resetted only by sample='1')

end if;

end process;


sh_en <= '1' when (cnt >= X"D6" and cnt < X"F5") else '0'; -- enables the serial clock when needed
sclk <= cnt(1); -- data is retrieved on from the A/D on the rising edge of 'sclk'
load <= not cnt(1); -- loads the bits on at a time in a register

convst <= '1' when (cnt = X"28" or rst = '1') else 
          '0' when cnt = X"02"; -- convst is active for about 1 us

rdy <= '1' when (sample = '1' or rst = '1') else -- rdy is reset when the osc_ctrl acknowledeges the active 'rdy' (by setting sample to '1')
       '0' when cnt = X"F5"; -- rdy is activated when the conversion is ready and data is available in the register

end Behavioral;