rate2div.vhd

来自「罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, Ph」· VHDL 代码 · 共 31 行

-- 'uspdiv' represents the 'microseconds per division' on the screen of the oscilloscope
-- 'uspdiv' is a linear function of 'srate': 'uspdiv' = 'srate' x period(mclk) x (nr of pixels between two vertical grid lines)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity rate2div is
    Port ( srate : in std_logic_vector(15 downto 0);
           uspdiv : out std_logic_vector(15 downto 0));
end rate2div;

architecture Behavioral of rate2div is

signal val : std_logic_vector(4 downto 0);

begin

-- the value of uspdiv is translated, rather than calculated for optimisation
--'uspdiv' = 'srate' x period(mclk) x (nr of pixels between two vertical grid lines)
--'uspdiv' = 'srate' x 20 ns x 40 ns/div
-- if 'srate'=250 ns (X"00FA") then 'uspdiv' = 250 ns x 20 ns x 40 ns/div = 200000 ns = 200 us
val <= "00001" when srate=X"00FA" else
       "00010" when srate=X"01F4" else
       "00100" when srate=X"03E8" else
       "01011" when srate=X"07D0" else
       "11001" when srate=X"0FA0";

uspdiv <= "00" & val & "000000000";

end Behavioral;