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XLXI_12_XLXI_1__n0004(XLXI_12_XLXI_1__n00041:O)| NONE(*)(XLXI_12_XLXI_1_rdy_3)| 5 |XLXI_2_XLXI_6_clkdiv:Q | NONE | 37 |XLXI_12_XLXI_1_rdy:Q | NONE | 81 |XLXI_13__n0005(XLXI_13_XNor_stagecy_rn_14:O)| NONE(*)(XLXI_13_sample)| 1 |XLXI_13_sample_rate_tuner_ssg_display_ms_cnt_15:Q| NONE | 2 |-----------------------------------+------------------------+-------+(*) These 4 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -6 Minimum period: 13.434ns (Maximum Frequency: 74.438MHz) Minimum input arrival time before clock: 13.135ns Maximum output required time after clock: 29.462ns Maximum combinational path delay: 20.617ns=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\projects\vhdl\doscope/_ngo -ucosc.ucf -p xc2s200e-pq208-6 dig_osc.ngc dig_osc.ngd Reading NGO file "D:/projects/vhdl/doscope/dig_osc.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "osc.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 42268 kilobytesWriting NGD file "dig_osc.ngd" ...Writing NGDBUILD log file "dig_osc.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s200epq208-6".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 3Logic Utilization: Total Number Slice Registers: 201 out of 4,704 4% Number used as Flip Flops: 190 Number used as Latches: 11 Number of 4 input LUTs: 495 out of 4,704 10%Logic Distribution: Number of occupied Slices: 667 out of 2,352 28% Number of Slices containing only related logic: 667 out of 667 100% Number of Slices containing unrelated logic: 0 out of 667 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 1,206 out of 4,704 25% Number used as logic: 495 Number used as a route-thru: 71 Number used for Dual Port RAMs: 640 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 34 out of 142 23% IOB Flip Flops: 1 IOB Latches: 1 Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 46,688Additional JTAG gate count for IOBs: 1,680Peak Memory Usage: 71 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "dig_osc_map.mrp" for details.Completed process "Map".Mapping Module dig_osc . . .
MAP command line:
map -intstyle ise -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o dig_osc_map.ncd dig_osc.ngd dig_osc.pcf
Mapping Module dig_osc: DONE
Started process "Place & Route".Constraints file: dig_osc.pcfLoading device database for application Par from file "dig_osc_map.ncd". "dig_osc" is an NCD, version 2.38, device xc2s200e, package pq208, speed -6Loading device for application Par from file '2s200e.nph' in environmentD:/development/Xilinx.Device speed data version: PRODUCTION 1.17 2004-06-25.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 34 out of 142 23% Number of LOCed External IOBs 34 out of 34 100% Number of SLICEs 667 out of 2352 28% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98ac42) REAL time: 3 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 3 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 3 secs Phase 5.8...............................Phase 5.8 (Checksum:d896c6) REAL time: 5 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 5 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 9 secs Writing design to file dig_osc.ncd.Total REAL time to Placer completion: 11 secs Total CPU time to Placer completion: 9 secs Phase 1: 5699 unrouted; REAL time: 11 secs Phase 2: 5461 unrouted; REAL time: 33 secs Phase 3: 1700 unrouted; REAL time: 36 secs Phase 4: 0 unrouted; REAL time: 38 secs Total REAL time to Router completion: 39 secs Total CPU time to Router completion: 34 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+| Clock Net | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+| mclk_BUFGP | Global | 32 | 0.073 | 0.492 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1__n0002 | Local | 1 | 0.000 | 2.150 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1_cnt<1> | Local | 16 | 0.241 | 3.558 |+----------------------------+----------+--------+------------+-------------+| XLXI_2_XLXI_6_clkdiv | Local | 21 | 1.569 | 3.439 |+----------------------------+----------+--------+------------+-------------+| XLXI_13__n0005 | Local | 9 | 0.000 | 2.419 |+----------------------------+----------+--------+------------+-------------+|XLXI_13_sample_rate_tune | | | | ||r_ssg_display_ms_cnt<15> | Local | 2 | 0.000 | 0.927 |+----------------------------+----------+--------+------------+-------------+|XLXI_12_XLXI_1_rdy | Local | 47 | 3.058 | 3.918 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1_rdy_4 | Local | 81 | 3.909 | 4.434 |+----------------------------+----------+--------+------------+-------------+|XLXI_13_sample_rate_tune | | | | || r_srate2uspdiv__n0085 | Local | 4 | 0.041 | 3.562 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1__n0004 | Local | 3 | 1.839 | 3.545 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1_rdy_3 | Local | 81 | 3.472 | 4.260 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1_rdy_2 | Local | 81 | 2.711 | 3.699 |+----------------------------+----------+--------+------------+-------------+| XLXI_12_XLXI_1_rdy_1 | Local | 81 | 2.864 | 3.748 |+----------------------------+----------+--------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 40 secs Total CPU time to PAR completion: 35 secs Peak Memory Usage: 71 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file dig_osc.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period". This generally indicates that there is an inconsistency between versions of the speed and device data files. Please check to ensure that the XILINX environment variable is set correctly, if the MYXILINX variable is set, make sure that it is pointing to patch files that are compatable with the version of software that the XILINX variable points to.Analysis completed Sat Jan 14 01:27:40 2006--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module dig_osc . . .
PAR command line: par -w -intstyle ise -ol std -t 1 dig_osc_map.ncd dig_osc.ncd dig_osc.pcf
PAR completed successfully
Started process "Programming File Generation Report".WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_12_XLXI_1__n0002 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_13_sample_rate_tuner_srate2uspdiv__n0085 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_12_XLXI_1__n0004 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.Completed process "Programming File Generation Report".
Project Navigator Auto-Make Log File-------------------------------------
deleting __projnav/acquisition_jhdparse_tcl.rspdeleting __projnav/dig_osc_jhdparse_tcl.rspdeleting __projnav/vga_display_jhdparse_tcl.rspdeleting dig_osc.vhfdeleting dig_osc.cmd_logdeleting vga_display.vhfdeleting vga_display.cmd_logdeleting acquisition.vhfdeleting acquisition.cmd_logdeleting dig_osc.lsodeleting dig_osc.syrdeleting dig_osc.prjdeleting dig_osc.sprjdeleting dig_osc.anadeleting dig_osc.stxdeleting dig_osc.cmd_logdeleting dig_osc.ngcdeleting dig_osc.ngrdeleting __projnav/ngdbuild.errdeleting __projnav/ednTOngd_tcl.rspdeleting d:\projects\vhdl\doscope/_ngodeleting dig_osc.ngddeleting dig_osc_ngdbuild.navdeleting dig_osc.blddeleting osc.ucf.untfdeleting dig_osc.cmd_logdeleting dig_osc_map.ncddeleting dig_osc.ngmdeleting dig_osc.pcfdeleting dig_osc.nc1deleting dig_osc.mrpdeleting dig_osc_map.mrpdeleting dig_osc.mdfdeleting __projnav/map.logdeleting dig_osc.cmd_logdeleting __projnav/ncdTOtwr_tcl.rspdeleting __projnav/posttrc.logdeleting dig_osc.twrdeleting dig_osc.twxdeleting dig_osc.tsideleting dig_osc.cmd_logdeleting __projnav/nc1TOncd_tcl.rspdeleting dig_osc.ncddeleting dig_osc.pardeleting dig_osc.paddeleting dig_osc_pad.txtdeleting dig_osc_pad.csvdeleting dig_osc.pad_txtdeleting dig_osc.dlydeleting reportgen.logdeleting dig_osc.xpideleting dig_osc.grfdeleting dig_osc.itrdeleting dig_osc_last_par.ncddeleting __projnav/par.logdeleting dig_osc.placed_ncd_trackerdeleting dig_osc.routed_ncd_trackerdeleting dig_osc.cmd_logdeleting __projnav/dig_osc_ncdTOut_tcl.rspdeleting __projnav/bitgen.rspdeleting bitgen.utdeleting dig_osc.utdeleting dig_osc.bgndeleting dig_osc.rbtdeleting dig_osc.lldeleting dig_osc.mskdeleting dig_osc.drcdeleting dig_osc.nkydeleting dig_osc.bitdeleting dig_osc.bindeleting dig_osc.iscdeleting dig_osc.cmd_logdeleting dig_osc.prjdeleting dig_osc.prjdeleting __projnav/dig_osc.xstdeleting ./xstdeleting __projnav/doscope.gfldeleting __projnav/doscope_flowplus.gflFinished cleaning up project
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