__projnav.log

罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, PhD提供的示波器开发全文挡及C,VHDL代码.

Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.3.03i - sch2vhdl G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Started process "View VHDL Functional Model".

Release 6.3.03i - sch2vhdl G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".



Started process "View VHDL Functional Model".

Release 6.3.03i - sch2vhdl G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/projects/vhdl/doscope/rate2div.vhd in Library work.
Entity <rate2div> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/ssgdisp.vhd in Library work.
Entity <ssgdisp> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/sr_tuner.vhd in Library work.
Entity <sr_tuner> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/s2pctrl.vhd in Library work.
Entity <s2pctrl> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/vga.vhd in Library work.
Entity <vga> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/vga_mem.vhd in Library work.
Entity <vgamemory> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/vga_display.vhf in Library work.
Entity <vga_display> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/acquisition.vhf in Library work.
Entity <SR8CE_MXILINX_acquisition> (Architecture <BEHAVIORAL>) compiled.
Entity <acquisition> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/osc_ctrl.vhd in Library work.
Entity <osc_ctrl> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/projects/vhdl/doscope/dig_osc.vhf in Library work.
Entity <dig_osc> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dig_osc> (Architecture <BEHAVIORAL>).
Entity <dig_osc> analyzed. Unit <dig_osc> generated.

Analyzing Entity <vga_display> (Architecture <behavioral>).
Entity <vga_display> analyzed. Unit <vga_display> generated.

Analyzing Entity <vga> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated.

Analyzing Entity <vgamemory> (Architecture <behavioral>).
WARNING:Xst:790 - D:/projects/vhdl/doscope/vga_mem.vhd line 29: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - D:/projects/vhdl/doscope/vga_mem.vhd line 37: Index value(s) does not match array range, simulation mismatch.
Entity <vgamemory> analyzed. Unit <vgamemory> generated.

Analyzing Entity <acquisition> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  XLXI_6_0" for instance <XLXI_6> in unit <acquisition>.
Entity <acquisition> analyzed. Unit <acquisition> generated.

Analyzing Entity <s2pctrl> (Architecture <behavioral>).
Entity <s2pctrl> analyzed. Unit <s2pctrl> generated.

Analyzing Entity <SR8CE_MXILINX_acquisition> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for instance <I_Q0> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q1> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q2> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q3> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q4> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q5> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q6> in unit <SR8CE_MXILINX_acquisition>.
    Set user-defined property "INIT =  0" for instance <I_Q7> in unit <SR8CE_MXILINX_acquisition>.
Entity <SR8CE_MXILINX_acquisition> analyzed. Unit <SR8CE_MXILINX_acquisition> generated.

Analyzing Entity <osc_ctrl> (Architecture <behavioral>).
Entity <osc_ctrl> analyzed. Unit <osc_ctrl> generated.

Analyzing Entity <sr_tuner> (Architecture <behavioral>).
Entity <sr_tuner> analyzed. Unit <sr_tuner> generated.

Analyzing Entity <rate2div> (Architecture <behavioral>).
Entity <rate2div> analyzed. Unit <rate2div> generated.

Analyzing Entity <ssgdisp> (Architecture <behavioral>).
Entity <ssgdisp> analyzed. Unit <ssgdisp> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ssgdisp>.
    Related source file is D:/projects/vhdl/doscope/ssgdisp.vhd.
    Found 16x7-bit ROM for signal <dig>.
    Found 1-of-4 decoder for signal <an>.
    Found 2-bit up counter for signal <digcnt>.
    Found 4-bit 4-to-1 multiplexer for signal <hex>.
    Found 16-bit up counter for signal <ms_cnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred   4 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <ssgdisp> synthesized.


Synthesizing Unit <rate2div>.
    Related source file is D:/projects/vhdl/doscope/rate2div.vhd.
WARNING:Xst:737 - Found 5-bit latch for signal <val>.
Unit <rate2div> synthesized.


Synthesizing Unit <sr_tuner>.
    Related source file is D:/projects/vhdl/doscope/sr_tuner.vhd.
    Found 1-bit register for signal <ce>.
    Found 1-bit register for signal <push_event<0>>.
    Found 16-bit register for signal <sr>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <sr_tuner> synthesized.


Synthesizing Unit <SR8CE_MXILINX_acquisition>.
    Related source file is D:/projects/vhdl/doscope/acquisition.vhf.
Unit <SR8CE_MXILINX_acquisition> synthesized.


Synthesizing Unit <s2pctrl>.
    Related source file is D:/projects/vhdl/doscope/s2pctrl.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <convst>.
WARNING:Xst:737 - Found 1-bit latch for signal <rdy>.
    Found 8-bit adder for signal <$n0000> created at line 35.
    Found 8-bit comparator greatequal for signal <$n0009> created at line 47.
    Found 8-bit comparator less for signal <$n0010> created at line 47.
    Found 8-bit register for signal <cnt>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <s2pctrl> synthesized.


Synthesizing Unit <vgamemory>.
    Related source file is D:/projects/vhdl/doscope/vga_mem.vhd.
    Found 640x8-bit dual-port distributed RAM for signal <mem>.
    -----------------------------------------------------------------------
    | aspect ratio       | 640-word x 8-bit                    |          |
    | clock              | connected to signal <wr>            | fall     |
    | write enable       | connected to internal node          | high     |
    | address            | connected to signal <w_addr>        |          |
    | dual address       | connected to signal <r_addr>        |          |
    | data in            | connected to signal <datain>        |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to internal node          |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Summary:
	inferred   1 RAM(s).
Unit <vgamemory> synthesized.


Synthesizing Unit <vga>.
    Related source file is D:/projects/vhdl/doscope/vga.vhd.
    Found 10-bit comparator equal for signal <$n0015> created at line 83.
    Found 10-bit comparator greater for signal <$n0038> created at line 88.
    Found 12-bit comparator less for signal <$n0039> created at line 88.
    Found 10-bit comparator less for signal <$n0040> created at line 94.
    Found 10-bit comparator greater for signal <$n0041> created at line 94.
    Found 10-bit comparator less for signal <$n0042> created at line 94.
    Found 10-bit comparator greater for signal <$n0043> created at line 94.
    Found 11-bit comparator greater for signal <$n0044> created at line 96.
    Found 10-bit comparator lessequal for signal <$n0045> created at line 96.
    Found 11-bit comparator greater for signal <$n0046> created at line 96.
    Found 10-bit comparator lessequal for signal <$n0047> created at line 96.
    Found 1-bit register for signal <clkdiv>.
    Found 10-bit up counter for signal <hc>.
    Found 10-bit up counter for signal <vc>.
    Found 1-bit register for signal <vsenable>.
    Found 10-bit subtractor for signal <x>.
    Found 10-bit subtractor for signal <y>.
    Found 10-bit adder for signal <ycoord>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred  11 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <osc_ctrl>.
    Related source file is D:/projects/vhdl/doscope/osc_ctrl.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <sample>.
    Found 16-bit comparator greatequal for signal <$n0005> created at line 110.
    Found 11-bit comparator less for signal <$n0008> created at line 93.
    Found 11-bit comparator greatequal for signal <$n0009> created at line 93.
    Found 10-bit adder for signal <$n0013> created at line 94.
    Found 10-bit register for signal <addrcnt>.
    Found 1-bit register for signal <d7>.
    Found 16-bit up counter for signal <samplecnt>.
    Found 1-bit register for signal <trigger>.
    Summary:
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <osc_ctrl> synthesized.


Synthesizing Unit <acquisition>.
    Related source file is D:/projects/vhdl/doscope/acquisition.vhf.
Unit <acquisition> synthesized.


Synthesizing Unit <vga_display>.
    Related source file is D:/projects/vhdl/doscope/vga_display.vhf.
Unit <vga_display> synthesized.


Synthesizing Unit <dig_osc>.
    Related source file is D:/projects/vhdl/doscope/dig_osc.vhf.
Unit <dig_osc> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# LUT RAMs                         : 1
 640x8-bit dual-port distributed RAM: 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 10-bit adder                      : 2
 10-bit subtractor                 : 2
 8-bit adder                       : 1
# Counters                         : 5
 16-bit up counter                 : 2
 10-bit up counter                 : 2
 2-bit up counter                  : 1
# Registers                        : 16
 10-bit register                   : 1
 1-bit register                    : 14
 16-bit register                   : 1
# Latches                          : 4
 1-bit latch                       : 3
 5-bit latch                       : 1
# Comparators                      : 16
 11-bit comparator greatequal      : 1
 11-bit comparator less            : 1
 16-bit comparator greatequal      : 1
 10-bit comparator lessequal       : 2
 11-bit comparator greater         : 2
 10-bit comparator greater         : 3
 10-bit comparator less            : 2
 12-bit comparator less            : 1
 10-bit comparator equal           : 1
 8-bit comparator less             : 1
 8-bit comparator greatequal       : 1
# Multiplexers                     : 2
 16-bit 2-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <osc_ctrl>: instances <Mcompar__n0008>, <Mcompar__n0009> of unit <LPM_COMPARE_15> and unit <LPM_COMPARE_16> are dual, second instance is removed

Optimizing unit <dig_osc> ...

Optimizing unit <vgamemory> ...

Optimizing unit <s2pctrl> ...

Optimizing unit <SR8CE_MXILINX_acquisition> ...

Optimizing unit <vga> ...

Optimizing unit <rate2div> ...

Optimizing unit <osc_ctrl> ...
Loading device for application Xst from file '2s200e.nph' in environment D:/development/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dig_osc, actual ratio is 13.
FlipFlop XLXI_13_addrcnt_2 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_3 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_1 has been replicated 1 time(s)
FlipFlop XLXI_2_XLXI_6_hc_0 has been replicated 1 time(s)
FlipFlop XLXI_2_XLXI_6_hc_1 has been replicated 1 time(s)
FlipFlop XLXI_2_XLXI_6_hc_2 has been replicated 1 time(s)
FlipFlop XLXI_2_XLXI_6_hc_3 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_4 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_7 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_8 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_5 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_6 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_0 has been replicated 16 time(s)
FlipFlop XLXI_13_addrcnt_9 has been replicated 1 time(s)
FlipFlop XLXI_13_addrcnt_2 has been replicated 16 time(s)
FlipFlop XLXI_13_addrcnt_3 has been replicated 16 time(s)
FlipFlop XLXI_13_addrcnt_1 has been replicated 16 time(s)
Latch XLXI_12_XLXI_1_rdy has been replicated 4 time(s)
FlipFlop XLXI_2_XLXI_6_hc_0 has been replicated 3 time(s)
FlipFlop XLXI_2_XLXI_6_hc_1 has been replicated 3 time(s)
FlipFlop XLXI_2_XLXI_6_hc_2 has been replicated 3 time(s)
FlipFlop XLXI_2_XLXI_6_hc_3 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                     476  out of   2352    20%  
 Number of Slice Flip Flops:           203  out of   4704     4%  
 Number of 4 input LUTs:               887  out of   4704    18%  
 Number of bonded IOBs:                 34  out of    146    23%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_12_XLXI_1_rdy_3:Q             | NONE                   | 81    |
XLXI_12_XLXI_1_cnt_1:Q             | NONE                   | 8     |
XLXI_13_sample_rate_tuner_srate2uspdiv__n0085(XLXI_13_sample_rate_tuner_srate2uspdiv__n008546:O)| NONE(*)(XLXI_13_sample_rate_tuner_srate2uspdiv_val_4)| 5     |
XLXI_12_XLXI_1_rdy_4:Q             | NONE                   | 81    |
XLXI_12_XLXI_1_rdy_2:Q             | NONE                   | 81    |
XLXI_12_XLXI_1_rdy_1:Q             | NONE                   | 81    |
XLXI_12_XLXI_1__n0002(XLXI_12_XLXI_1__n00021:O)| NONE(*)(XLXI_12_XLXI_1_convst)| 1     |
mclk                               | BUFGP                  | 59    |