vga_display.sch

罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, PhD提供的示波器开发全文挡及C,VHDL代码.

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "spartan2e"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL XLXN_1(7:0)
        SIGNAL XLXN_2(9:0)
        SIGNAL XLXN_3
        SIGNAL w_addr(9:0)
        SIGNAL wr
        SIGNAL mclk
        SIGNAL blu
        SIGNAL grn
        SIGNAL red
        SIGNAL vs
        SIGNAL hs
        SIGNAL datain(7:0)
        SIGNAL rst
        PORT Input w_addr(9:0)
        PORT Input wr
        PORT Input mclk
        PORT Output blu
        PORT Output grn
        PORT Output red
        PORT Output vs
        PORT Output hs
        PORT Input datain(7:0)
        PORT Input rst
        BEGIN BLOCKDEF vga
            TIMESTAMP 2006 1 13 18 58 59
            RECTANGLE N 64 -448 320 0 
            LINE N 64 -416 0 -416 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
            LINE N 320 -416 384 -416 
            LINE N 320 -352 384 -352 
            LINE N 320 -288 384 -288 
            LINE N 320 -224 384 -224 
            LINE N 320 -160 384 -160 
            LINE N 320 -96 384 -96 
            LINE N 320 -32 384 -32 
            RECTANGLE N 320 -44 384 -20 
        END BLOCKDEF
        BEGIN BLOCKDEF vgamemory
            TIMESTAMP 2006 1 13 19 12 58
            RECTANGLE N 64 -384 320 0 
            LINE N 64 -352 0 -352 
            LINE N 64 -288 0 -288 
            LINE N 64 -224 0 -224 
            LINE N 64 -160 0 -160 
            RECTANGLE N 0 -172 64 -148 
            LINE N 64 -96 0 -96 
            RECTANGLE N 0 -108 64 -84 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
            LINE N 320 -352 384 -352 
            RECTANGLE N 320 -364 384 -340 
        END BLOCKDEF
        BEGIN BLOCK XLXI_6 vga
            PIN mclk mclk
            PIN data(7:0) XLXN_1(7:0)
            PIN rd XLXN_3
            PIN hs hs
            PIN vs vs
            PIN red red
            PIN grn grn
            PIN blu blu
            PIN addr(9:0) XLXN_2(9:0)
        END BLOCK
        BEGIN BLOCK XLXI_7 vgamemory
            PIN rst rst
            PIN rd XLXN_3
            PIN wr wr
            PIN r_addr(9:0) XLXN_2(9:0)
            PIN w_addr(9:0) w_addr(9:0)
            PIN datain(7:0) datain(7:0)
            PIN dataout(7:0) XLXN_1(7:0)
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN BRANCH XLXN_1(7:0)
            WIRE 1888 1312 2000 1312
            WIRE 2000 1312 2000 1376
            WIRE 2000 1376 2112 1376
        END BRANCH
        BEGIN BRANCH XLXN_2(9:0)
            WIRE 1440 1504 1504 1504
            WIRE 1440 1504 1440 1728
            WIRE 1440 1728 2576 1728
            WIRE 2496 1376 2576 1376
            WIRE 2576 1376 2576 1728
        END BRANCH
        BEGIN BRANCH XLXN_3
            WIRE 1424 816 1424 1376
            WIRE 1424 1376 1504 1376
            WIRE 1424 816 2560 816
            WIRE 2560 816 2560 992
            WIRE 2496 992 2560 992
        END BRANCH
        BEGIN BRANCH wr
            WIRE 1232 1440 1504 1440
        END BRANCH
        BEGIN BRANCH blu
            WIRE 2496 1312 2832 1312
        END BRANCH
        BEGIN BRANCH grn
            WIRE 2496 1248 2832 1248
        END BRANCH
        BEGIN BRANCH red
            WIRE 2496 1184 2832 1184
        END BRANCH
        BEGIN BRANCH vs
            WIRE 2496 1120 2832 1120
        END BRANCH
        BEGIN BRANCH hs
            WIRE 2496 1056 2816 1056
        END BRANCH
        IOMARKER 2816 1056 hs R0 28
        IOMARKER 2832 1120 vs R0 28
        IOMARKER 2832 1184 red R0 28
        IOMARKER 2832 1248 grn R0 28
        IOMARKER 2832 1312 blu R0 28
        BEGIN BRANCH w_addr(9:0)
            WIRE 1232 1568 1504 1568
        END BRANCH
        BEGIN BRANCH datain(7:0)
            WIRE 1232 1632 1504 1632
        END BRANCH
        BEGIN INSTANCE XLXI_6 2112 1408 R0
        END INSTANCE
        BEGIN BRANCH mclk
            WIRE 1232 992 2096 992
            WIRE 2096 992 2112 992
        END BRANCH
        IOMARKER 1232 1440 wr R180 28
        IOMARKER 1232 1568 w_addr(9:0) R180 28
        IOMARKER 1232 1632 datain(7:0) R180 28
        IOMARKER 1232 992 mclk R180 28
        BEGIN INSTANCE XLXI_7 1504 1664 R0
        END INSTANCE
        BEGIN BRANCH rst
            WIRE 1248 1312 1504 1312
        END BRANCH
        IOMARKER 1248 1312 rst R180 28
    END SHEET
END SCHEMATIC