📄 net_nic.c
字号:
/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK INTERFACE CARD
*
* Atmel MACB
* for the
* AT91SAM7X256, AT91SAM9260, AT91SAM9263, & AVR32
*
* Filename : net_nic.c
* Version : V1.90
* Programmer(s) : EHS
* BAN (Converted AT91SAM7x256 driver to generic MACB driver)
*********************************************************************************************************
* Note(s) : (1) This driver supports the Atmel MACB EMAC, often referred to as "MACB" or "EMACB" in
* Atmel documentation, for the following Atmel processors (and possibly others) :
*
* Atmel Corporation (ATMEL; http://www.atmel.com)
* (a) AVR32 (ATMEL AVR32; Revision 7684AX-AVR32-Nov06 )
* (b) AT91SAM7X256 (ATMEL AT91SAM7X; Revision 6120F-ATARM-03-Oct-06)
* (c) AT91SAM9260 (ATMEL AT91SAM9260; Revision 6221D-ATARM-12-Mar-07)
* (d) AT91SAM9263 (ATMEL AT91SAM9263; Revision 6249B-ATARM-14-Dec-06)
*
* (2) REQUIREs Ethernet Network Interface Layer located in the following network directory :
*
* \<Network Protocol Suite>\IF\Ether\
*
* where
* <Network Protocol Suite> directory path for network protocol suite.
*
* (3) All processor- or hardware-specific functions, such as clearing an interrupt, which
* might be identical between any two of these platforms, are now located in net_bsp.c.
*
* (4) Since the MACB module is integrated into either an ARM or AVR32 microcontroller,
* the endianness of the registers is the same as the CPU, which is little-endian by
* default.
*********************************************************************************************************
* TO DO(s) : (1) Add support for jumbo frames.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#define NET_NIC_MODULE
#include <net.h>
/*
*********************************************************************************************************
* ATMEL MACB RECEIVE BUFFER DESCRIPTOR
*********************************************************************************************************
*/
#define EMAC_RXBUF_ADDRESS_MASK (0xFFFFFFFC) /* Addr of Rx Descriptor Buf's (wrap/ownership ignored */
#define EMAC_RXBUF_ADD_WRAP DEF_BIT_01 /* This is the last buffer in the ring. */
#define EMAC_RXBUF_SW_OWNED DEF_BIT_00 /* Software owns the buffer. */
#define EMAC_RXBUF_LEN_MASK (0x00000FFF) /* Length of frame including FCS. (12 bits) */
#define EMAC_RXBUF_SOF_MASK DEF_BIT_14 /* Start of frame mask */
#define EMAC_RXBUF_EOF_MASK DEF_BIT_15 /* End of frame mask */
#define EMAC_RXBUF_OFF_MASK (0x03 << 12) /* Data offset mask (up to three bytes possible) */
#define EMAC_TXBUF_ADD_WRAP DEF_BIT_30 /* This is the last buffer in the ring. */
#define EMAC_TXBUF_TX_SIZE_MASK (0x000007FF) /* Length of frame including FCS. (11 bits) */
#define EMAC_TXBUF_ADD_LAST DEF_BIT_15 /* This is the last buffer for the current frame */
#define EMAC_TXBUF_STATUS_USED DEF_BIT_31 /* Status Used Bit. Indicates when a buf has been read */
/*
*********************************************************************************************************
* ATMEL MACB REGISTERS
*
* Note(s) : (1) See ATMEL AT91SAM7X256, AT91SAM9260, or AVR32 documentation for register summary.
*
* (2) Since the MACB module is integrated into either an ARM or AVR32 microcontroller,
* the endianness of the registers is the same as the CPU, which is little-endian by default.
*
* (3) The base address of the MACB registers, MACB_BASE, must be defined in net_bsp.h
*
* (4) To protect MACB register accesses during multi-thread operation, registers MUST be
* accessed in critical sections &/or mutual exclusion.
*
* (a) For read-modify-write register access OR multiple-register-access sequences; critical
* sections &/or mutual exclusion enclosing the entire register access/sequence is REQUIRED.
*********************************************************************************************************
*/
/* -------- CONFIGURATION REGISTERS --------------- */
#define MACB_NCR (*(volatile CPU_INT32U *)(MACB_BASE + 0x00)) /* EMAC Control Register */
#define MACB_NCFGR (*(volatile CPU_INT32U *)(MACB_BASE + 0x04)) /* EMAC Configuration Register */
#define MACB_NSR (*(volatile CPU_INT32U *)(MACB_BASE + 0x08)) /* EMAC Status Register */
#define MACB_TSR (*(volatile CPU_INT32U *)(MACB_BASE + 0x14)) /* EMAC Transmit Status Register */
#define MACB_RBQP (*(volatile CPU_INT32U *)(MACB_BASE + 0x18)) /* EMAC Receive Buffer Queue Pointer */
#define MACB_TBQP (*(volatile CPU_INT32U *)(MACB_BASE + 0x1C)) /* EMAC Transmit Buffer Queue Pointer */
#define MACB_RSR (*(volatile CPU_INT32U *)(MACB_BASE + 0x20)) /* EMAC Receive Status Register */
#define MACB_ISR (*(volatile CPU_INT32U *)(MACB_BASE + 0x24)) /* EMAC Interrupt Status Register */
#define MACB_IER (*(volatile CPU_INT32U *)(MACB_BASE + 0x28)) /* EMAC Interrupt Enable Register */
#define MACB_IDR (*(volatile CPU_INT32U *)(MACB_BASE + 0x2C)) /* EMAC Interrupt Disable Register */
#define MACB_IMR (*(volatile CPU_INT32U *)(MACB_BASE + 0x30)) /* EMAC Interrupt Mask Register */
#define MACB_MAN (*(volatile CPU_INT32U *)(MACB_BASE + 0x34)) /* EMAC PHY Maintenance Register */
#define MACB_PTR (*(volatile CPU_INT32U *)(MACB_BASE + 0x38)) /* EMAC Pause Time Register */
/* -------- STATISTIC REGISTERS ------------------- */
#define MACB_PFR (*(volatile CPU_INT32U *)(MACB_BASE + 0x3C)) /* Pause Frames Received Register */
#define MACB_FTO (*(volatile CPU_INT32U *)(MACB_BASE + 0x40)) /* Frames Transmitted OK Register */
#define MACB_SCF (*(volatile CPU_INT32U *)(MACB_BASE + 0x44)) /* Single Collision Frame Register */
#define MACB_MCF (*(volatile CPU_INT32U *)(MACB_BASE + 0x48)) /* Multiple Collision Frame Register */
#define MACB_FRO (*(volatile CPU_INT32U *)(MACB_BASE + 0x4C)) /* Frames Received OK Register */
#define MACB_FCSE (*(volatile CPU_INT32U *)(MACB_BASE + 0x50)) /* Frame Check Sequence Error Register */
#define MACB_ALE (*(volatile CPU_INT32U *)(MACB_BASE + 0x54)) /* Alignment Error Register */
#define MACB_DTF (*(volatile CPU_INT32U *)(MACB_BASE + 0x58)) /* Deferred Transmission Frame Register */
#define MACB_LCOL (*(volatile CPU_INT32U *)(MACB_BASE + 0x5C)) /* Late Collision Register */
#define MACB_ECOL (*(volatile CPU_INT32U *)(MACB_BASE + 0x60)) /* Excessive Collision Register */
#define MACB_TUND (*(volatile CPU_INT32U *)(MACB_BASE + 0x64)) /* Transmit Underrun Error Register */
#define MACB_CSE (*(volatile CPU_INT32U *)(MACB_BASE + 0x68)) /* Carrier Sense Error Register */
#define MACB_RRE (*(volatile CPU_INT32U *)(MACB_BASE + 0x6C)) /* Receive Resource Error Register */
#define MACB_ROV (*(volatile CPU_INT32U *)(MACB_BASE + 0x70)) /* Receive Jabber Register */
#define MACB_RSE (*(volatile CPU_INT32U *)(MACB_BASE + 0x74)) /* Undersize Frame Register */
#define MACB_ELE (*(volatile CPU_INT32U *)(MACB_BASE + 0x78)) /* Excessive Length Error Register */
#define MACB_RJA (*(volatile CPU_INT32U *)(MACB_BASE + 0x7C)) /* Receive Jabbers Register */
#define MACB_USF (*(volatile CPU_INT32U *)(MACB_BASE + 0x80)) /* Undersize Frame Register */
#define MACB_STE (*(volatile CPU_INT32U *)(MACB_BASE + 0x84)) /* SQE Test Error Register */
#define MACB_RLE (*(volatile CPU_INT32U *)(MACB_BASE + 0x88)) /* Received Length Field Mismatch Register */
/* -------- ADDRESS REGISTERS --------------------- */
#define MACB_HRB (*(volatile CPU_INT32U *)(MACB_BASE + 0x90)) /* Hash Register Bottom [31: 0] Register */
#define MACB_HRT (*(volatile CPU_INT32U *)(MACB_BASE + 0x94)) /* Hash Register Top [63:32] Register */
#define MACB_SA1L (*(volatile CPU_INT32U *)(MACB_BASE + 0x98)) /* Specific Address 1 Bottom Register */
#define MACB_SA1H (*(volatile CPU_INT32U *)(MACB_BASE + 0x9C)) /* Specific Address 1 Top Register */
#define MACB_SA2L (*(volatile CPU_INT32U *)(MACB_BASE + 0xA0)) /* Specific Address 2 Bottom Register */
#define MACB_SA2H (*(volatile CPU_INT32U *)(MACB_BASE + 0xA4)) /* Specific Address 2 Top Register */
#define MACB_SA3L (*(volatile CPU_INT32U *)(MACB_BASE + 0xA8)) /* Specific Address 3 Bottom Register */
#define MACB_SA3H (*(volatile CPU_INT32U *)(MACB_BASE + 0xAC)) /* Specific Address 3 Top Register */
#define MACB_SA4L (*(volatile CPU_INT32U *)(MACB_BASE + 0xB0)) /* Specific Address 4 Bottom Register */
#define MACB_SA4H (*(volatile CPU_INT32U *)(MACB_BASE + 0xB4)) /* Specific Address 4 Top Register */
/* ----- ADDITIONAL CONFIGURATION REGISTERS ------- */
#define MACB_TID (*(volatile CPU_INT32U *)(MACB_BASE + 0xB8)) /* Type ID Checking Register */
#define MACB_USRIO (*(volatile CPU_INT32U *)(MACB_BASE + 0xC0)) /* User Input/Output Register */
#define MACB_WOL (*(volatile CPU_INT32U *)(MACB_BASE + 0xC4)) /* Wake on LAN */
/*
*********************************************************************************************************
* ATMEL MACB REGISTER BITS
*********************************************************************************************************
*/
/* ---------------------- MACB_NCR bits ----------------------- */
#define MACB_NCR_LB DEF_BIT_00 /* Loopback. When set, loopback signal is at high level. */
#define MACB_NCR_LLB DEF_BIT_01 /* Loopback local. */
#define MACB_NCR_RE DEF_BIT_02 /* Receive enable. */
#define MACB_NCR_TE DEF_BIT_03 /* Transmit enable. */
#define MACB_NCR_MPE DEF_BIT_04 /* Management port enable. */
#define MACB_NCR_CLRSTAT DEF_BIT_05 /* Clear statistics registers. */
#define MACB_NCR_INCSTAT DEF_BIT_06 /* Increment statistics registers. */
#define MACB_NCR_WESTAT DEF_BIT_07 /* Write enable for statistics registers. */
#define MACB_NCR_BP DEF_BIT_08 /* Back pressure. */
#define MACB_NCR_TSTART DEF_BIT_09 /* Start Transmission. */
#define MACB_NCR_THALT DEF_BIT_10 /* Transmission Halt. */
#define MACB_NCR_TPFR DEF_BIT_11 /* Transmit pause frame */
#define MACB_NCR_TZQ DEF_BIT_12 /* Transmit zero quantum pause frame */
/* ---------------------- MACB_NCFGR bits --------------------- */
#define MACB_NCFGR_SPD DEF_BIT_00 /* Speed. */
#define MACB_NCFGR_FD DEF_BIT_01 /* Full duplex. */
#define MACB_NCFGR_JFRAME DEF_BIT_03 /* Jumbo Frames. */
#define MACB_NCFGR_CAF DEF_BIT_04 /* Copy all frames. */
#define MACB_NCFGR_NBC DEF_BIT_05 /* No broadcast. */
#define MACB_NCFGR_MTI DEF_BIT_06 /* Multicast hash event enable */
#define MACB_NCFGR_UNI DEF_BIT_07 /* Unicast hash enable. */
#define MACB_NCFGR_BIG DEF_BIT_08 /* Receive 1522 bytes. */
#define MACB_NCFGR_EAE DEF_BIT_09 /* External address match enable. */
#define MACB_NCFGR_CLK ((CPU_INT32U) 3 << 10)
#define MACB_NCFGR_CLK_HCLK_8 ((CPU_INT32U) 0 << 10) /* HCLK divided by 8 */
#define MACB_NCFGR_CLK_HCLK_16 ((CPU_INT32U) 1 << 10) /* HCLK divided by 16 */
#define MACB_NCFGR_CLK_HCLK_32 ((CPU_INT32U) 2 << 10) /* HCLK divided by 32 */
#define MACB_NCFGR_CLK_HCLK_64 ((CPU_INT32U) 3 << 10) /* HCLK divided by 64 */
#define MACB_NCFGR_RTY DEF_BIT_12
#define MACB_NCFGR_PAE DEF_BIT_13
#define MACB_NCFGR_RBOF ((CPU_INT32U) 3 << 14)
#define MACB_NCFGR_RBOF_OFFSET_0 ((CPU_INT32U) 0 << 14) /* no offset from start of receive buffer */
#define MACB_NCFGR_RBOF_OFFSET_1 ((CPU_INT32U) 1 << 14) /* one byte offset from start of receive buffer */
#define MACB_NCFGR_RBOF_OFFSET_2 ((CPU_INT32U) 2 << 14) /* two bytes offset from start of receive buffer */
#define MACB_NCFGR_RBOF_OFFSET_3 ((CPU_INT32U) 3 << 14) /* three bytes offset from start of receive buffer */
#define MACB_NCFGR_RLCE DEF_BIT_16 /* Receive Length field Checking Enable */
#define MACB_NCFGR_DRFCS DEF_BIT_17 /* Discard Receive FCS */
#define MACB_NCFGR_EFRHD DEF_BIT_18
#define MACB_NCFGR_IRXFCS DEF_BIT_19 /* Ignore RX FCS */
/* ---------------------- MACB_NSR bits ----------------------- */
#define MACB_NSR_LINKR DEF_BIT_00
#define MACB_NSR_MDIO DEF_BIT_01
#define MACB_NSR_IDLE DEF_BIT_02
/* ---------------------- MACB_TSR bits ----------------------- */
#define MACB_TSR_UBR DEF_BIT_00
#define MACB_TSR_COL DEF_BIT_01
#define MACB_TSR_RLES DEF_BIT_02
#define MACB_TSR_TGO DEF_BIT_03 /* Transmit Go */
#define MACB_TSR_BEX DEF_BIT_04 /* Buffers exhausted mid frame */
#define MACB_TSR_COMP DEF_BIT_05
#define MACB_TSR_UND DEF_BIT_06
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -