test.asm

The evergoing number of electrical & electronic products, as well as the widespread use of modern ho

;File Name: scidac0.asm
;Description: Outputs 2 Sine Waves on the EVM DAC - DAC0 and DAC1
.include "x24x_app.h"
;I/O Mapped EVM Registers
DAC0 		.set 0000h 				;Input Data Register for DAC0
DAC1 		.set 0001h 				;Input Data Register for DAC1
DAC2 		.set 0002h 				;Input Data Register for DAC2
DAC3 		.set 0003h 				;Input Data Register for DAC3
DACUPDATE   .set 0004h 				;Update Register

;Constant definitions
LENGTH1  	.set 00007h 			;Length of the data stream to be
;transmitted
LENGTH2 	.set 16

;Variable definitions
.bss 		GPR0,1 					;General purpose register.
.bss 		DAC0VAL,1 				;DAC0 Channel Value
.bss 		DAC1VAL,1 				;DAC1 Channel Value
.bss 		DAC2VAL,1 				;DAC2 Channel Value
.bss 		DAC3VAL,1 				;DAC3 Channel Value

;Initialized Transmit Data for Interrupt Service Routine
.data
READY
.word 0052h 			;Hex equivalent of ASCII character 'R'
.word 0065h 			;Hex equivalent of ASCII character 'e'
.word 0061h 			;Hex equivalent of ASCII character 'a'
.word 0064h 			;Hex equivalent of ASCII character 'd'
.word 0079h 			;Hex equivalent of ASCII character 'y'
.word 000dh 			;Hex equivalent of ASCII <CR>
.word 0000h 			;Hex equivalent of ASCII NULL
INVALID_IP 
.word 000ah 			;Hex equivalent of ASCII (NEW LINE)
.word 0049h 			;Hex equivalent of ASCII character 'I'
.word 006Eh 			;Hex equivalent of ASCII character 'n'
.word 0076h 			;Hex equivalent of ASCII character 'v'
.word 0061h 			;Hex equivalent of ASCII character 'a'
.word 006Ch 			;Hex equivalent of ASCII character 'l'
.word 0069h 			;Hex equivalent of ASCII character 'i'
.word 0064h 			;Hex equivalent of ASCII character 'd'
.word 0020h 			;Hex equivalent of ASCII (SPACE)
.word 0069h 			;Hex equivalent of ASCII character 'i'
.word 006Eh 			;Hex equivalent of ASCII character 'n'
.word 0070h 			;Hex equivalent of ASCII character 'p'
.word 0075h 			;Hex equivalent of ASCII character 'u'
.word 0074h 			;Hex equivalent of ASCII character 't'
.word 000dh 			;Hex equivalent of ASCII <CR>
.word 0000h 			;Hex equivalent of ASCII NULL

;Vector address declarations
.sect ".vectors"
RSVECT 	B START 					;PM 0 Reset 	Vector 1
INT1 		B INT1_ISR 				;PM 2 Int level 1 4
INT2 		B PHANTOM 				;PM 4 Int level 2 5
INT3 		B PHANTOM 				;PM 6 Int level 3 6
INT4 		B PHANTOM 				;PM 8 Int level 4 7
INT5		B PHANTOM 				;PM A Int level 5 8
INT6 		B PHANTOM 				;PM C Int level 6 9
RESERVED 	B PHANTOM 				;PM E (Analysis Int) 10
SW_INT8 	B PHANTOM 				;PM 10 User S/W int -
SW_INT9 	B PHANTOM 				;PM 12 User S/W int -
SW_INT10 	B PHANTOM 				;PM 14 User S/W int -
SW_INT11 	B PHANTOM 				;PM 16 User S/W int -
SW_INT12	B PHANTOM 				;PM 18 User S/W int -
SW_INT13 	B PHANTOM 				;PM 1A User S/W int -
SW_INT14 	B PHANTOM 				;PM 1C User S/W int -
SW_INT15 	B PHANTOM 				;PM 1E User S/W int -
SW_INT16 	B PHANTOM 				;PM 20 User S/W int -
TRAP 		B PHANTOM 				;PM 22 Trap vector -
NMINT 	B PHANTOM 				;PM 24 Non maskable Int 3
EMU_TRAP B PHANTOM 				;PM 26 Emulator Trap 2
SW_INT20 B PHANTOM 				;PM 28 User S/W int -
SW_INT21 B PHANTOM 				;PM 2A User S/W int -
SW_INT22 B PHANTOM 				;PM 2C User S/W int -
SW_INT23 B PHANTOM 				;PM 2E User S/W int -

;M A I N C O D E - starts here
.text
NOP
START
SETC 		INTM 			;Disable interrupts
CLRC 		SXM 				;Clear Sign Extension Mode
CLRC 		OVM 				;Reset Overflow Mode
CLRC 		CNF 				;Config Block B0 to Data mem.
SPLK 		#0001h,IMR 		;Mask all core interrupts except INT1
LACC 		IFR 				;Read Interrupt flags
SACL 		IFR 				;Clear all interrupt flags
LDP 		#00E0h
SPLK 		#006Fh, WDCR 	;Disable Watchdog if VCCP=5V
KICK_DOG 					;Reset Watchdog counter
;Initialize B2 RAM to zero's.
LAR 		AR2,#B2_SADDR 	;AR2 -> B2 start address
MAR 		*,AR2 			;Set ARP=AR2
ZAC 						;Set ACC = 0
RPT 		#1fh 			;Set repeat cntr for 31+1 loops
SACL 		*+ 				;Write zeros to B2 RAM
;Initialize B0 RAM to zero's.
LAR 		AR2,#B0_SADDR 	;AR2 -> B2 start address
MAR 		*,AR2 			;Set ARP=AR2
ZAC 						;Set ACC = 0
RPT 		#255 			;Set repeat cntr for 31+1 loops
SACL 		*+ 				;Write zeros to B2 RAM
;Initialize B1 RAM to zero's.
LAR 		AR2,#B1_SADDR 	;AR2 -> B2 start address
MAR 		*,AR2 			;Set ARP=AR2
ZAC 						;Set ACC = 0
RPT 		#255 			;Set repeat cntr for 31+1 loops
SACL 		*+ 				;Write zeros to B2 RAM
;Initialize DATAOUT with data to be transmitted.
LAR 		AR2,#B1_SADDR 	;Reset AR2 -> B1 start address
RPT 		#(LENGTH1+LENGTH2-1)
;Set repeat counter for
;LENGTH1+LENGTH2 loops
BLPD 		#READY,*+ 		;loads B2 with TXDATA
;INITIALIZATION OF INTERRUPT DRIVEN SCI ROUTINE
SCI_INIT
LDP 		#00E0h
SPLK 		#0036h,SCICCR 	;1 stop bit, odd parity, 7 char bit
;async mode, idle-line protocol
SPLK 		#0013h, SCICTL1 ;Enable TX, RX, internal SCICLK,
;Disable RX ERR, SLEEP, TXWAKE
SPLK 		#0002h, SCICTL2 ;Enable RX INT,disable TX INT
SPLK 		#0000h, SCIHBAUD
SPLK 		#0040h, SCILBAUD;Baud Rate=19200 b/s (10 MHz SYSCLK)
SPLK 		#0022h, SCIPC2 	;Enable TXD & RXD pins
SPLK 		#0033h, SCICTL1 ;Relinquish SCI from Reset.
LAR 		AR0, #SCITXBUF 	;Load AR0 with SCI_TX_BUF address
LAR 		AR1, #SCIRXBUF 	;Load AR1 with SCI_RX_BUF address
LAR 		AR2, #B2_SADDR 	;Load AR2 with TX data start address
;INITIALIZATION OF PLL MODULE
LDP 		#00E0h
SPLK		#0000000001000001b,CKCR0 
;CLKMD=PLL,Disable SYSCLK=CPUCLK/2
SPLK 		#0000000010111011b,CKCR1
;CLKIN(OSC)=10MHz,CPUCLK=20MHz
SPLK 		#0000000011000001b,CKCR0 
;CLKMD=PLL Enable,SYSCLK=CPUCLK/2
SPLK 		#0100000011000000b,SYSCR 
;CLKOUT=CPUCLK
;SYSCR - System Control Register

;Event Manager Module Reset
LDP 		#232 			;DP=232 Data Page for the Event Manager
SPLK 		#0000h,GPTCON 	;Clear General Purpose Timer Control
SPLK 		#0000h,T1CON 	;Clear GP Timer 1 Control
SPLK 		#0000h,T2CON 	;Clear GP Timer 2 Control
SPLK 		#0000h,T3CON 	;Clear GP Timer 3 Control
SPLK 		#0000h,COMCON 	;Clear Compare Control
SPLK 		#0000h,ACTR 	;Clear Full Compare Action Control
;Register
SPLK 		#0000h,SACTR 	;Clear Simple Compare Action Control 
;Register
SPLK 		#0000h,DBTCON 	;Clear Dead-Band Timer Control Register
SPLK 		#0000h,CAPCON 	;Clear Capture Control
SPLK 		#0FFFFh,EVIFRA 	;Clear Interrupt Flag Register A
SPLK 		#0FFFFh,EVIFRB 	;Clear Interrupt Flag Register B
SPLK 		#0FFFFh,EVIFRC 	;Clear Interrupt Flag Register C
SPLK 		#0000h,EVIMRA 	;Clear Event Manager Mask Register A
SPLK 		#0000h,EVIMRB 	;Clear Event Manager Mask Register B
SPLK 		#0000h,EVIMRC 	;Clear Event Manager Mask Register C

;INITIALIZATION OF EVENT MANAGER MODULE
T1COMPARE 	.set 0 			;Compare value not necessary
T1PERIOD 	.set 610 		;T1PERIOD set to value equivalent to
;32.768kHz with CPULCLK = 20MHz
QT1PERIOD .set 0001h 		;Q15 period value for period of
;32.768kHz
.text
LDP 		#232 			;DP=232, Data Page for Event Manager
;Addresses
SPLK 		#T1COMPARE,T1CMPR
 							;Initialize GP Timer 1 Compare Register
SPLK 		#0000001010101b,GPTCON
SPLK 		#T1PERIOD,T1PR 	;Initialize GP Timer 1 Period Register
SPLK 		#0000h,T1CNT 	;Initialize GP Timer 1
SPLK 		#0000h,T2CNT 	;Initialize GP Timer 2
SPLK 		#0000h,T3CNT 	;Initialize GP Timer 3
SPLK 		#0001000000000100b,T1CON
SPLK 		#0000000000000000b,T2CON
 	;Not Used
SPLK 		#0000000000000000b,T3CON 	
;Not Used
;Initialize Variables for Generation of Sine Wave on DAC
;The DAC module requires that wait states be generated for proper operation.
LDP 		#0000h 			;Set Data Page Pointer to
;0000h, Block B2
SPLK 		#4h,GPR0 		;Set Wait State Generator for
OUT 		GPR0,WSGR 		;Program Space, 0WS
;Data Space, 0WS
;I/O Space, 1WS
.bss 		TABLE,1 			;Keeps address of the
;pointer in the SINE Table
.bss 		TOPTABLE,1 		;Keeps the reset value for the pointer
.bss 		COMPARET1,1 	;A register to do calculations since the
;T1CMPR register is double buffered
.bss 		REMAINDER,1 	;Remainder of the MODREGx values
.bss 		VALUE,1 			;SINE Table Value
.bss 		NEXTVALUE,1 	;Next entry in the SINE Table
.bss 		DIFFERENCE,1 	;Difference between Entries
.bss 		FREQSTEP1,1 	;Frequency modulation of the
;1st sine wave
.bss 		MODREG1,1 		;Rolling Modulo Register for
;1st sine wave
.bss 		MAG1,1 			;Magnitude of the frequency
;for 1st sine wave
.bss 		FREQSTEP2,1 	;Frequency modulation of the
;2nd sine wave
.bss 		MODREG2,1 		;Rolling Modulo Register for
;2nd sine wave
.bss 		MAG2,1 			;Magnitude of the frequency
;for 2nd sine wave
.bss 		TEMP,1 			;Register to hold temporary values
.bss 		NEW_VALUE,1 	;New value to load into
;the appropriate register
.bss 		PREV_VALUE,1 	;Previous value before being changed
.bss 		DIVISOR,1
.text
NOP
SPLK 		#0000h,TABLE
SPLK 		#STABLE,TOPTABLE
SPLK 		#1000,FREQSTEP1 ;Controls the frequency for DAC0
SPLK 		#0000h,MODREG1 	;Sets the starting point
SPLK 		#7FFFh,MAG1 	;Maximum value, Q15
SPLK 		#1000,FREQSTEP2 ;Controls the frequency for DAC1
SPLK 		#0000h,MODREG2 	;Sets the starting point
SPLK 		#7FFFh,MAG2 	;Maximum value, Q15
SPLK 		#0000h,TEMP 	;Initialize temporary register
SPLK 		#0000h,NEW_VALUE;Initialize new value
SPLK 		#0000h,PREV_VALUE
 	;Initialize previous value
SPLK 		#0000h,DIVISOR 	;Initialize the maximum register
SPLK		#0000h,QUOTIENT ;Initialize the quotient
LAR 		AR0, #SCITXBUF 	;Load AR0 with SCI_TX_BUF address
LAR 		AR1, #SCIRXBUF 	;Load AR1 with SCI_RX_BUF address
LAR 		AR2, #B1_SADDR 	;Load AR2 with TX data start address
LAR 		AR3, #B0_SADDR
CLRC 		INTM
WAITING
LDP 		#232
BIT 		EVIFRA,BIT7 	;Polling routine to wait for
BCND 		WAITING,NTC 	;T1PINT Flag to be Set
;Generate Sine Wave
SINE
LDP 		#0
LACC 		MODREG1 			;ACC loaded with the counting register
ADD 		FREQSTEP1 		;Counting Register increased by
;specific step
SACL 		MODREG1 			;Store the updated counter value
LACC		MODREG1,8 		;Reload the new ctr value but
;shift left by 8 bits
SACH 		TABLE 			;Store the high bit pointer to
									;lookup table
SFR 						;Shift the value to the right
;convert to Q15
AND 		#07FFFh 			;Make sure the Q15 value is positive
SACL 		REMAINDER 		;Store the fractional value of
;the counting register
LACC		TABLE 			;Load the accumulator with the
;proper index value
ADD 		TOPTABLE 		;Displace the ACC with the
;starting address
TBLR 		VALUE 			;Read the value from the table
;and store into VALUE
ADD			#1 				;Increment the ACC to the next address
TBLR 		NEXTVALUE 		;Read the next value from the
;table and
LACC		NEXTVALUE 		;Load the ACC with NEXTVALUE
SUB			VALUE 			;Subtract the previous value
SACL 		DIFFERENCE 		;Store the difference between
;the values
LT 			DIFFERENCE 		;Load the TREG with DIFFERENCE
MPY 		REMAINDER 		;Multiply the DIFFERENCE with REMAINDER
PAC 						;Move the product to the ACC
SACH 		REMAINDER,1 	;Store the upper byte and shift
;left by 1, Q15
LACC 		REMAINDER 		;Load ACC with new REMAINDER
ADD 		VALUE 			;Add VALUE to get the new
;interpolated value
SACL 		VALUE 			;Store the interpolated value
;into VALUE
LT 			VALUE 			;Load the TREG with the new
;interpolated VALUE
MPY 		MAG1 			;Multiply VALUE by a magnitude
PAC 						;Move the product to ACC
SACH 		DAC0VAL,1 		;Store the new value, shift to get Q15
;The following section performs the necessary calculations for the
;second sine wave
LACC 		MODREG2 			;ACC loaded with the counting register
ADD 		FREQSTEP2 		;Counting Register increased by
;specific step
SACL 		MODREG2 			;Store the updated the counter value
LACC 		MODREG2,8 		;Reload the new ctr value, shift left
;by 8 bits
SACH 		TABLE 			;Store the high bit as pointer to
;lookup table
SFR 						;Shift the value to the right convert
;to Q15
AND 		#07FFFh 			;Make sure the Q15 value is positive
SACL 		REMAINDER 		;Store the fractional value of the
;counting register
LACC 		TABLE 			;Load the accumulator with the proper
;index value
ADD 		TOPTABLE 		;Displace the ACC with the starting
;address
TBLR 		VALUE 			;Read the value from the table and
;store into VALUE
ADD 		#1 				;Increment the ACC to the next
;address
TBLR 		NEXTVALUE 		;Read the next value from the table
;and store
LACC 		NEXTVALUE 		;Load the ACC with NEXTVALUE
SUB 		VALUE 			;Subtract the previous value
SACL 		DIFFERENCE 		;Store the difference between the value
LT 			DIFFERENCE 		;Load the TREG with DIFFERENCE
MPY 		REMAINDER 		;Multiply the DIFFERENCE with REMAINDER
PAC 						;Move the product to the ACC
SACH 		REMAINDER,1 	;Store the upper byte and shift left
;by 1, Q15
LACC 		REMAINDER 		;Load ACC with new REMAINDER
ADD 		VALUE 			;Add VALUE to get the new
;interpolated value
SACL 		ALUE 			;Store the interpolated value into
;VALUE
LT 			LUE 				;Load the TREG with the new