auregs.h

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#ifndef __AUREGS_H__
#define __AUREGS_H__

#if !defined(WIN32)
#include "config.h"
#include "regmap.h"
#include "types.h"
#endif

/* DMA pcm mapping flag setting */
#if CONFIG == CONFIG_COMBO_SVCD
#define DMA_PCM_MAPPING         (1<<6)
#elif CONFIG == CONFIG_COMBO_VCD
#define DMA_PCM_MAPPING         (0<<6)
#endif

/*
 * AUDIO hardware register file
 */
#define RF_AU_RESET         (regs0->audio_reg[ 0])
#define RF_VCD_VERSION      (regs0->audio_reg[ 1])
#define RF_IS_LAYER3        (regs0->audio_reg[ 2])
#define RF_READ_CMD         (regs0->audio_reg[ 3])
#define RF_WRITE_CMD        (regs0->audio_reg[ 4])
#define RF_RS_CMD           (regs0->audio_reg[ 5])
#define RF_IMDCT_CMD        (regs0->audio_reg[ 6])
#define RF_RS_CH_NUM        (regs0->audio_reg[ 7])
#define RF_RS_BUF_LEN       (regs0->audio_reg[ 8])	// 6 bits
#define RF_RS_RD_ANCHOR     (regs0->audio_reg[ 9])
//#define RF_APCM_BUF_LEN     (regs0->audio_reg[10])
#define RF_GREG0            (regs0->audio_reg[11])
#define RF_EMPHASIS_BIT     (regs0->audio_reg[12])
#define RF_TEST_MODE        (regs0->audio_reg[13])
#define RF_CMD_FLAG         (regs0->audio_reg[14])	// 1 : active, 0 : end
#define RF_REQ_SP_COUNT     (regs0->audio_reg[15])
#define RF_REQ_SP_COUNT_INC (regs0->audio_reg[16])
#define RF_CD_MODE          (regs0->audio_reg[17])	// 1/0 (no RS/RS)
#define RF_EQ_ON            (regs0->audio_reg[18])
#define RF_FULL_BAND_EQ     (regs0->audio_reg[19])
#define RF_EQ_AMP_ADR       (regs0->audio_reg[20])
#define RF_RS_CMD_CLR       (regs0->audio_reg[21])
#define RF_FFT_NO_EQ        (regs0->audio_reg[22])
#define RF_NRJ_FN           (regs0->audio_reg[23])
#define RF_NRJ_ENG_TH_LOW   (regs0->audio_reg[24])
#define RF_NRJ_CHK_NUM      (regs0->audio_reg[25])
#define RF_NRJ_FLAG         (regs0->audio_reg[26])
#define RF_NRJ_ENG_TH_HIGH  (regs0->audio_reg[27])
#define RF_MP2_SYN          (regs0->audio_reg[28])

#if !defined(WIN32)
/*
 * AUDIO/PCM hardware SRAM
 */
#define AU_RAM0             ((volatile UINT32 *)((BYTE *)regs0+0x2800))	// R/W, 128 words
#define AU_RAM1             ((volatile UINT32 *)((BYTE *)regs0+0x2a00))	// R/W, 64 words
#define AU_RAM2             ((volatile UINT32 *)((BYTE *)regs0+0x3000))	// WO, 128 words
#endif

/*
 * parameters in RAM0
 */
#define PAR_BASE            36
#define PAR_READ_ADR        (PAR_BASE+ 0)
#define PAR_WRITE_ADR       (PAR_BASE+ 1)
#define PAR_RS0_IN_ADR      (PAR_BASE+ 2)
#define PAR_RS1_IN_ADR      (PAR_BASE+ 3)
#define PAR_RS2_IN_ADR      (PAR_BASE+ 4)
#define PAR_RS3_IN_ADR      (PAR_BASE+ 5)
#define PAR_REQ0_IDX_ADR    (PAR_BASE+ 6)
#define PAR_REQ1_IDX_ADR    (PAR_BASE+ 7)
#define PAR_IMDCT_IN_ADR    (PAR_BASE+ 8)
#define PAR_IMDCT_OLD_ADR   (PAR_BASE+ 9)
#define PAR_IMDCT_OUT_ADR   (PAR_BASE+10)
#define PAR_PCML0_ADR       (PAR_BASE+11)	// syn outout for L ch
#define PAR_PCMR0_ADR       (PAR_BASE+12)	// syn outout for R ch
#define PAR_VI0_ADR         (PAR_BASE+13)
#define PAR_VI1_ADR         (PAR_BASE+14)
#define PAR_EQ0_ADR         (PAR_BASE+15)
#define PAR_EQ1_ADR         (PAR_BASE+16)

/*
 * PCM hardware register file
 */
#define PCM_RF_BASE         32
// for write
#define RF_PCM_SF           (regs0->audio_reg[PCM_RF_BASE+ 0])
#define RF_PCM_KEY_OFFSET   (regs0->audio_reg[PCM_RF_BASE+ 1])	// 9-bit signed number
#define RF_PCM_ADCTRL       (regs0->audio_reg[PCM_RF_BASE+ 2])
#define RF_PCM_RESET        (regs0->audio_reg[PCM_RF_BASE+ 3])
#define RF_PCM_BUF_LEN      (regs0->audio_reg[PCM_RF_BASE+ 4])
#define RF_PCM_COUNT_INC    (regs0->audio_reg[PCM_RF_BASE+ 5])
#define RF_PCM_CFG          (regs0->audio_reg[PCM_RF_BASE+ 6])	// configuring DAC
#define RF_PCM_MODE         (regs0->audio_reg[PCM_RF_BASE+ 7])
#define RF_PCM_FRM_ADDR     (regs0->audio_reg[PCM_RF_BASE+ 8])	// fade-out start address
#define RF_PCM_KEY_ADDR     (regs0->audio_reg[PCM_RF_BASE+ 9])
#define RF_PCM_RAMP_HGT     (regs0->audio_reg[PCM_RF_BASE+10])	// ramp-down
#define RF_PCM_RAMP_FN      (regs0->audio_reg[PCM_RF_BASE+12])
#define RF_PCM_MODE_CHG     (regs0->audio_reg[PCM_RF_BASE+13])
#define RF_PCM_AMP          (regs0->audio_reg[PCM_RF_BASE+14])
#define RF_PCM_HQ_ECO       (regs0->audio_reg[PCM_RF_BASE+15])
#define RF_PCM_R2UPDT       (regs0->audio_reg[PCM_RF_BASE+16])
#define RF_PCM_KEY_CNT      (regs0->audio_reg[PCM_RF_BASE+17])
#define RF_AD_ENG_CLR       (regs0->audio_reg[PCM_RF_BASE+18])
#define RF_ECO_RST          (regs0->audio_reg[PCM_RF_BASE+19])
#define RF_AD_FIR_FN        (regs0->audio_reg[PCM_RF_BASE+56])
#define RF_PCM_BALANCE      (regs0->audio_reg[PCM_RF_BASE+57])
// for read
#define RF_PCM_CNT          (regs0->audio_reg[PCM_RF_BASE+20])
#define RF_PCM_CF_READ      (regs0->audio_reg[PCM_RF_BASE+21])
#define RF_PCM_RP0          (regs0->audio_reg[PCM_RF_BASE+22])
#define RF_PCM_RP1          (regs0->audio_reg[PCM_RF_BASE+23])
#define RF_PCM_RP2          (regs0->audio_reg[PCM_RF_BASE+24])
#define RF_PCM_CF_FLAG      (regs0->audio_reg[PCM_RF_BASE+25])	// Set RF_PCM_KEY_CNT will raise this flag. Pulled down after crossfading ends.
#define RF_RAM2_WRT_DIS     (regs0->audio_reg[PCM_RF_BASE+26])
#define RF_WP               (regs0->audio_reg[PCM_RF_BASE+27])
#define RF_RS_PCM_PTR       (regs0->audio_reg[PCM_RF_BASE+28])
#define RF_WP1              (regs0->audio_reg[PCM_RF_BASE+29])
#define RF_PCM_OV           (regs0->audio_reg[PCM_RF_BASE+30])
#define RF_PCM_EMPTY        (regs0->audio_reg[PCM_RF_BASE+31])
#define RF_AD_ENG_METER     (regs0->audio_reg[PCM_RF_BASE+32])
#define RF_RAMP_FLAG        (regs0->audio_reg[PCM_RF_BASE+33])
#define RF_NRJ_MET_FLAG     (regs0->audio_reg[PCM_RF_BASE+34])

/*
 * RAM2 layout
 */
#define RAM2_PCML0_BASE     ( 0)	// 8 16-bit words
#define RAM2_PCMR0_BASE     ( 8)	// 8 16-bit words
#define RAM2_PCML1_BASE     (16)	// 8 16-bit words
#define RAM2_PCMR1_BASE     (24)	// 8 16-bit words
#define RAM2_ECO_BASE       (32)	// 16 16-bit words
#define RAM2_P2S_BASE       (48)	// 16 16-bit words
#define RAM2_PAR_BASE       (64)	// PCM hardware parameters
#define RAM2_FIR_BASE       (80)	// 16-bit 40-tap FIR filter
#define RAM2_AD_BASE        (120)	// 8 16-bit words

/*
 * parameters in RAM2 based on RAM2_PAR_BASE
 * addresses and sizes are all in units of 8 samples.
 */
#define R2_PCML0_ADR        (RAM2_PAR_BASE+ 0)
#define R2_PCMR0_ADR        (RAM2_PAR_BASE+ 1)
#define R2_PCML1_ADR        (RAM2_PAR_BASE+ 2)
#define R2_PCMR1_ADR        (RAM2_PAR_BASE+ 3)
#define R2_ECO_FUDU_ADR     (RAM2_PAR_BASE+ 4)
#define R2_PCM1_SIZE        (RAM2_PAR_BASE+ 5)
#define R2_ECO_FUDU_SIZE    (RAM2_PAR_BASE+ 6)
#define R2_PCM_X            (RAM2_PAR_BASE+ 7)
#define R2_PCM_Y            (RAM2_PAR_BASE+ 8)
#define R2_ECO_X            (RAM2_PAR_BASE+ 9)
#define R2_ECO_Y            (RAM2_PAR_BASE+10)
//#define R2_PCM_AMP          (RAM2_PAR_BASE+11)
#define R2_ECO_AMP          (RAM2_PAR_BASE+12)
#define R2_RAMP_L           (RAM2_PAR_BASE+13)
#define R2_RAMP_R           (RAM2_PAR_BASE+14)
#define R2_RP2_UPDT_ADR     (RAM2_PAR_BASE+15)

#endif //!__AUREGS_H__