regmap.h

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    UINT32  tdm_din2;                           // 237
    UINT32  tdm_din3;                           // 238

    UINT32  reg_unused[17];             // 239-255

    UINT32  audio_reg[256];             // for audio

    UINT32  unused[1536];                   // 6K space
    /*
     ** risc dma memory
     */
    WorkBuf dma_mem;

}
RegisterFile;


/*
**  Video
*/
#define RF_CODING_EXT0_PROGRESSIVE_FRAME    (1<<0)
#define RF_CODING_EXT0_CHROMA_420_TYPE      (1<<1)
#define RF_CODING_EXT0_REPEAT_FIRST_FIELD   (1<<2)
#define RF_CODING_EXT0_ALTERNATE_SCAN       (1<<3)
#define RF_CODING_EXT0_INTRA_VLC_FORMAT     (1<<4)
#define RF_CODING_EXT0_Q_SCALE_TYPE     (1<<5)
#define RF_CODING_EXT0_CONCEAL_MOTION_VECTORS   (1<<6)
#define RF_CODING_EXT0_FRAME_PRED_FRAME_DCT (1<<7)
#define RF_CODING_EXT0_TOP_FIELD_FIRST      (1<<8)
#define RF_CODING_EXT0_PICTURE_STRUCTURE    (0x03<<9)
#define RF_CODING_EXT0_INTRA_DC_PRECISION   (0x03<<11)
#define RF_CODING_EXT0_LAST_PICTURE     (1<<14)
#define RF_CODING_EXT0_SECOND_FIELD     (1<<15)

#define ext0_pic_struct(x)  (((x)>>9)&0x03)


/*
**  Task Priority Entries
*/
#define RF_TASK_PR                      0
#define RF_TASK_SR                      1
#define RF_TASK_OR                      2
#define RF_TASK_AUP                     3
#define RF_TASK_MR                      4
#define RF_TASK_MW                      5
#define RF_TASK_VR                      6
#define RF_TASK_CDAW                    7
#define RF_TASK_RD                      8
#define RF_TASK_DDIM24                  9
#define RF_TASK_DDIM16                  10
#define RF_TASK_LBC                     11
#define RF_TASK_DPDM24                  12
#define RF_TASK_DPDM16                  13

/*
**  Display Output Tweaking
*/
#define RF_VOUT_SWAP_CBCR       (1<<1)
#define RF_VOUT_SWAP_LC         (1<<2)

/*
**  Display Status
*/
#define RF_Display_OSDRegion        0x00ff
#define RF_Display_FieldNo      0x8000
#define RF_Display_VSyncB       0x4000
#define RF_Display_HSyncB       0x2000
#define RF_Display_FieldEnd     0x1000


#define DISPLAY_STATUS  regs0->display_status
#define IsVSync                 ((DISPLAY_STATUS & RF_Display_VSyncB)==0)
#define IsHSync                 ((DISPLAY_STATUS & RF_Display_HSyncB)==0)
#define IsTopField          ((DISPLAY_STATUS & RF_Display_FieldNo)==0)
#define IsBottomField       ((DISPLAY_STATUS & RF_Display_FieldNo))
#define IsFieldEnd          ((DISPLAY_STATUS & RF_Display_FieldEnd))

#define WAIT_VSYNC          do {} while (!IsVSync)
#if CONFIG == CONFIG_COMBO_VCD
#define WAIT_DISABLE_VSYNC      do { polling_cddsp(); } while (!IsVSync)
#endif

#define RF_Video_VPicEnd        0x0001
#define RF_Video_VTblErr        0x0002
#define RF_Video_VRunErr        0x0004
#define RF_Video_VSliceErr      0x0008
#define RF_Video_VErr           0x8000

/*
**  RISC Picture Start
*/
#define RF_RI_PicStart          0x0001
#define IsRPicStart (regs0->pic_start & RF_RI_PicStart)

/*
**  VLD Decoding Status
*/
#define VLD_STATUS  (regs0->vld_status)
#define IsVPicEnd   (VLD_STATUS & RF_Video_VPicEnd)
#define IsVRunErr   (VLD_STATUS & RF_Video_VRunErr)
#define IsVTblErr   (VLD_STATUS & RF_Video_VTblErr)
#define IsVErr      (VLD_STATUS & RF_Video_VErr)

#define RF_CodingExt1_ForRef0       (0<<1)
#define RF_CodingExt1_ForRef1       (1<<1)

#define RF_CodingExt1_Reconst0      (0<<2)
#define RF_CodingExt1_Reconst1      (1<<2)
#define RF_CodingExt1_ReconstB      (2<<2)


#define RF_CODING_EXT1_FORWARD_REF0 (0<<1)
#define RF_CODING_EXT1_FORWARD_REF1 (1<<1)

#define RF_CODING_EXT1_RECONST_REF0 (0<<2)
#define RF_CODING_EXT1_RECONST_REF1 (1<<2)
#define RF_CODING_EXT1_RECONST_B    (2<<2)

#define RF_CODING_EXT1_FIELDID      (1<<4)


/*
**  TIMER
*/
#define RF_TIMER_SRC_SYSCLK     (0<<14)
#define RF_TIMER_SRC_STC        (1<<14)
#define RF_TIMER_SRC_RTC        (2<<14)
#define RF_TIMER_SRC_TIMER      (3<<14)
#define RF_TIMER_RUN_ON         (1<<13)
#define RF_TIMER_RUN_OFF        (0<<13)
#define RF_TIMER_GO_ON          (1<<11)
#define RF_TIMER_GO_OFF         (0<<11)
#define RF_TIMER_MASK           (0x3ff)

#define TIMER_CONFIG_STC        ( RF_TIMER_SRC_STC  \
                    | RF_TIMER_RUN_ON   \
                    | RF_TIMER_GO_ON)

#define TIMER_CONFIG_100ms      ( TIMER_CONFIG_STC | (9000-1))
#define TIMER_CONFIG_10ms       ( TIMER_CONFIG_STC | (900-1))
#define TIMER_CONFIG_4ms        ( TIMER_CONFIG_STC | (360-1))
#define TIMER_CONFIG_1ms        ( TIMER_CONFIG_STC | (90-1))

#define TIMER_CONFIG_90k(n)     ( TIMER_CONFIG_STC | (n-1))


/*
**  OGT control flags
*/
#define RF_OGT_ENABLE           (1<<0)
#define RF_OGT_CVD          (1<<3)
#define RF_OGT_SVCD         (0<<3)
#define RF_OGT_HL0_ENABLE       (1<<1)
#define RF_OGT_HL1_ENABLE       (1<<2)
#define RF_OGT_ERR_DISABLE      (1<<5)

#if 1
/*
**  VPP control
*/
#define RF_FILTER_VERTICALx1        (0<<6)
#define RF_FILTER_VERTICALx2        (1<<6)
#define RF_FILTER_VERTICALx4        (2<<6)
#define RF_FILTER_VERTICALx8        (3<<6)

#define RF_FILTER_INT_1to1      (0<<4)
#define RF_FILTER_INT_6to5      (1<<4)
#define RF_FILTER_INT_5to6      (2<<4)
#define RF_FILTER_INT_4to3      (3<<4)

#define RF_FILTER_INT_x2_toggle     (1<<3)

#define RF_FILTER_INT_field     (0<<2)
#define RF_FILTER_INT_frame     (1<<2)

#define RF_FILTER_disable       (0<<1)
#define RF_FILTER_enable        (1<<1)

#define RF_H_EXP_CIF_disable        (0<<9)
#define RF_H_EXP_CIF_enable     (1<<9)

#define RF_H_EXP_disable        (0<<8)
#define RF_H_EXP_enable         (1<<8)

#define RF_H_EXP_8_1                    (RF_H_EXP_enable | 0x10 | RF_H_EXP_CIF_enable)
#define RF_H_EXP_4_1                    (RF_H_EXP_enable | 0x20 | RF_H_EXP_CIF_enable)
#define RF_H_EXP_3_2                    (RF_H_EXP_enable | 0x2b | RF_H_EXP_CIF_disable)
//#define       RF_H_EXP_2_1                    (RF_H_EXP_enable | 0x40 | RF_H_EXP_CIF_enable)
#define RF_H_EXP_2_1                    (RF_H_EXP_disable | 0x40 | RF_H_EXP_CIF_enable)
#define RF_H_EXP_1_1                    (RF_H_EXP_disable)

#define RF_H_EXP_480                    (RF_H_EXP_3_2)
#define RF_H_EXP_352                    (RF_H_EXP_CIF_enable)
#endif



/*
**  Display Control
*/
#define SetDisplayPicture(x)        (regs0->dis_pic_id = (x))
#define SetDisplayStartX(x)     (regs0->dis_x_start = (x))
#define SetDisplayStartY(y)     (regs0->dis_y_start = (y))
#define SetDisplayStart(x,y)        {SetDisplayStartX(x); SetDisplayStartY(y);}
#define SetDisplaySizeX(w)      (regs0->dis_x_size = (w))
#define SetDisplaySizeY(h)      (regs0->dis_y_size = (h))
#define SetDisplaySize(w,h)     {SetDisplaySizeX(w); SetDisplaySizeY(h);}


#define RF_LINESIZE_352         0
#define RF_LINESIZE_704         1
#define RF_LINESIZE_256         2
#define RF_LINESIZE_512         3
#define RF_LINESIZE_480         4
#define RF_LINESIZE_64          7

/*
**  IR control
*/
#define RF_IR_RX_flag           0x0001
#define IR_STATUS           (regs0->ir_status)
#define IsIrFull            (IR_STATUS & RF_IR_RX_flag)

/*
**  CDDSP Control/Status
*/
#define RF_CDDSP_RESET          0x0001
#define RF_CDDSP_STOP           0x0002
#define RF_CDDSP_PAUSE          0x0004
#define RF_CDDSP_SEEK           0x0008
#define RF_CDDSP_CONT           0x0010//jhuang 2003/3/10 add

#define RF_CDDSP_CRC_ERROR      0x0001
#define RF_CDDSP_CRC_ERROR_LAST     0x0002
#define RF_CDDSP_CRC_ERROR_MASK     0x0003

#define SET_CDDSP_VX(x)         (regs0->cddsp_vx = (x))
#define SET_CDDSP_VY(y)         (regs0->cddsp_vy = (y))
//#define SET_CDDSP_LIMIT(y)      (regs0->cddsp_limit = (y))

#define GET_CDDSP_VY()          (regs0->cddsp_vy)
#define GET_CDDSP_VX()          (regs0->cddsp_vx)

/*
**
*/
#define RF_DSP24_RESET          (1<<0)
#define RF_DSP24_STALL          (1<<1)

/*
** EPP status
*/
#define RF_EPP_IN_FULL          (1<<3)
#define RF_EPP_IN_EMPTY         (1<<2)
#define RF_EPP_OUT_FULL         (1<<1)
#define RF_EPP_OUT_EMPTY        (1<<0)

#define RF_Video_MPEG2_flag     0x08


/*
**  VIDEO   VIDEO   VIDEO   VIDEO   VIDEO   VIDEO   VIDEO   VIDEO
*/

#define RF_VIDEO_COMPRESS_888       0x00
#define RF_VIDEO_COMPRESS_766       0x01
#define RF_VIDEO_COMPRESS_666       0x02
#define RF_VIDEO_COMPRESS_8655      0x03


/*
**  AUDIO_CLOCK AUDIO_CLOCK AUDIO_CLOCK AUDIO_CLOCK
*/
#define RF_AUDCLK_08192000      0   /* 000:  8,192,000 Hz   */
#define RF_AUDCLK_11289600      1   /* 001: 11,289,360 Hz   */
#define RF_AUDCLK_12288000      2   /* 01x: 12,288,000 Hz   */
#define RF_AUDCLK_16934400      4   /* 000: 16,934,400 Hz   */
#define RF_AUDCLK_18432000      5   /* 000: 18,432,000 Hz   */


/*
** DSA control
*/
#define IOP_DSA

#define RF_DSA_TX_flag                  0x4000
#define RF_DSA_RX_flag                  0x8000
#define RF_DSA_RESET_flag               0x2000

#ifdef IOP_DSA
#define IsDsaTxEmpty    ((regs0->iop_data[4] & RF_DSA_TX_flag)==0)
#define SetDsaTxFull    (regs0->iop_data[4]  |= (RF_DSA_TX_flag))
#define SetDsaRxEmpty   (regs0->iop_data[4]  &= (~(RF_DSA_RX_flag)))
#define IsDsaRxFull     ((regs0->iop_data[4] & RF_DSA_RX_flag))
#define SetDsaReset     (regs0->iop_data[4]  |= (RF_DSA_RESET_flag))
#else
#define IsDsaTxEmpty    ((regs0->dsa_status & RF_DSA_TX_flag)==0)
#define IsDsaTxFull     ((regs0->dsa_status & RF_DSA_TX_flag))
#define IsDsaRxEmpty    ((regs0->dsa_status & RF_DSA_RX_flag)==0)
#define IsDsaRxFull     ((regs0->dsa_status & RF_DSA_RX_flag))
#endif

/*
** AGDC config
*/
#define RF_AGDC_B_SMALL 0
#define RF_AGDC_B_LARGE 1

#define RF_COMPRESS_888     0
#define RF_COMPRESS_866     1
#define RF_COMPRESS_666     2
#define RF_COMPRESS_8655    3


/*
** define register file
*/
#ifdef  UNIX
EXTERN volatile RegisterFile *regfile0;
EXTERN volatile RegisterFile *regs0;

#define InitRegFile()   (regs0 = regfile0)
#else
#ifdef  GLOBAL_REGISTER
register volatile RegisterFile *regs0 asm("22");    /* you must init this! */

#define InitRegFile()   (regs0 = (volatile RegisterFile *)RGST_OFFSET)
#else
#define regs0           ((volatile RegisterFile *)RGST_OFFSET)
#define InitRegFile()   {}
#endif
#endif

#endif/*__REGMAP_DVD_H*/