config.h

代码有点长,需细心阅读,仅供影音视听类产品的开发人员参考

#ifndef __CONFIG_H
#define __CONFIG_H
#include "set.h"                                //jhuang 2002/7/12 10:29PM
 
/* ENDIAN SELECT */
#define BIG           0
#define LITTLE        1
#define ENDIAN        LITTLE

#define CLK27       0
#define CLK337      1
#define CLK405      2
#define CLK54       3
#define CLK675      4
#define CLK81       5

//#define SYSCLK        CLK27
//#define SYSCLK        CLK337
//#define SYSCLK        CLK405
//#define SYSCLK        CLK54
#define SYSCLK            CLK675
//#define SYSCLK        CLK81

/*
** configuration of mpeg2/mpeg1 core controller
*/
#define CONFIG_VCD    0
#define CONFIG_SVCD   1
#define CONFIG_DVD    2
#define CONFIG_COMBO_SVCD 3
#define CONFIG_COMBO_VCD  4

#define CONFIG      CONFIG_COMBO_VCD

#define SUPPORT_MIXED_MODE_DISC         1
#define SUPPORT_CHECK_PIC_DECODE        1
#define SUPPORT_IR      1
#define SUPPORT_VFD     1
#define SUPPORT_MP3     1
#define SUPPORT_OSD     1

/*
** servo 
*/

#if defined(SONY_SERVO)||defined(PANASONIC_SERVO)
#define AUDIO_XCLK_OUT                  //ZHX 092003
#endif

#define EDO_REDUCE
#define NEW_SKATE_TRACK_HANDLE
#define SUPPORT_CODE_COMPRESS_EDO       1
//#define SUPPORT_SCREEN_SAFE             1
//#define SUPPORT_MP3STOP_SCREEN_SAFE           //ZHX 092203 Bug!
//#define SUPPORT_STORE_PSD_TBL           1     //ZHX 090603
//#define SUPPORT_JPG                     1
#define SUPPORT_ALL_PLAY_LIST           1
#define SUPPORT_SERACH_2_PLAY           1
#define SUPPORT_FF_ACROSS_TRACK         1 
#define CDDA_USE_LOGO                  //ZHX 110303  

#ifndef SUPPORT_EPP_DBG
#define SUPPORT_EPP     0
#define UART_DEBUG      0
#else
#define SUPPORT_EPP     1
#define UART_DEBUG      1
#endif

#define SUPPORT_DSA     1

#define SUPPORT_PU8550B 1

#if defined(mips) || defined(__LX4080)
#define PRODUCTION
#else
#if defined(arm) || defined(__arm)
#define ARM_EVM
#define inline  __inline
#endif
#endif

/*
**
*/
#ifdef  mips
#define GLOBAL_REGISTER
#if     (CONFIG==CONFIG_DVD)
#define RGST_OFFSET     0xafff0000
#elif   (CONFIG==CONFIG_SVCD)
#define RGST_OFFSET     0x00510000
#elif   (CONFIG==CONFIG_VCD)
#define RGST_OFFSET     0x00510000
#elif   (CONFIG==CONFIG_COMBO_SVCD)
#define RGST_OFFSET     0xafff0000
#else   /* (CONFIG==CONFIG_COMBO_VCD) */
#define RGST_OFFSET     0xafff0000
#endif
#else
#ifdef  ARM_EVM
#define RGST_OFFSET     0x0B800000
#else
#define RGST_OFFSET     0x0B800000
#endif
#endif



//#ifdef    EMULATION
//#define   RTC_TICKS   (12)      // for emulation 8MHz
//#else
#define RTC_TICKS   (100)               // for real 54MHz
//#endif

//#define   QUANT_ZIGZAG
#define OLDAGDC     0

#define POLLING_VIDEO_DECODE
#define CHECK_PARSING_BARRIER
#if  CONFIG==CONFIG_COMBO_SVCD
#define PIC_INFO_SDRAM
#define PIC_INFO_ENTRIES    64
#else
#define PIC_INFO_ENTRIES    16
#endif

//#define   PAL
//#define   NTSC
#define PARSE_GOP
//#define   PARSE_USER_DATA

#define FRAME_DECODING
//#define FIELD_DECODING

#define MEMORY_LARGE                    0x80
#define MEMORY_SMALL                    0x00

#define MEMORY_PAL                      0x04
#define MEMORY_NTSC                     0x00
#define MEMORY_NTSCPAL_MASK             (MEMORY_PAL | MEMORY_NTSC)

#define MEMORY_ROM_MASK                 0x03
#define MEMORY_ROM_NONE                 0x00
#define MEMORY_ROM_1M                   0x01
#define MEMORY_ROM_2M                   0x02
#define MEMORY_ROM_4M                   0x03

#define TRP_LEN             2<<0
#define TRCD                2<<2
#define TCP                 0<<4
#define TCAS                0<<5
//#define TCAS              0<<5
#define TRAS_LEN            0<<6
#define TCP_LEN             0<<8
#define TCSR_LEN            1<<9
#define TRSH_LEN            0<<10
#define PAD_SEL             0<<11
#define CAS_DLY             5<<12
#define EDO_CONFIG (TRP_LEN|TRCD|TCP|TCAS|TRAS_LEN|TCP_LEN|TCSR_LEN|TRSH_LEN|PAD_SEL|CAS_DLY)
#define SYSTEM_LEN_MAX      2324

#define CDDSP_CRC_RETRY     1
#define CDDSP_RETRY_LOW     16
#define CDDSP_RETRY     20
#define CDDSP_GOBACK        -6
#define CDDSP_RESTART_TIME  (2*RTC_TICKS)

/*
** GNU c specific definitions.
*/
#ifdef  __GNUC__
#define ENABLE_INLINE
#if defined(ARM_EVM)
#define __value_in_regs
#define ENABLE_INLINE
#endif
#endif

#ifdef  ENABLE_INLINE
#ifdef  ARM_EVM
#define INLINE  __inline
#else
#define INLINE  inline
#endif
#else
#define INLINE
#endif

/*
** decoding start criteria
*/
#define VBV_START       512         /* ROWs to start first decoding */
#define VBV_START_PICTURE   (PIC_INFO_ENTRIES/2)    /* PICs to start first decoding */

/*
** cd restart criteria
*/
//#define   VBV_LOW         1024    /* ROWs to restart CD       */
#define VBV_PIC_LOW     12          /* PICs to restart CD       */

//#define   ABV_LOW         32  /* ROWs to restart CD       */

/*
** parsing pause criteria
*/
#define VBV_LIMIT       2               /* ROWs to stop parsing     */
#define ABV_LIMIT       2               //1//4
#define CBV_LIMIT       3               //8

/*
** DMA batch, deprecated
*/
#define DMA_BATCH       64

/*
** system input buffer (0-63)
*/
#define SRV_IN_BUF      0
#define SRV_IN_BATCH        DMA_BATCH

/*
** video output buffer (64-95)
*/
#define VIDEO_OUT_BUF       (SRV_IN_BUF+SRV_IN_BATCH)
#define VIDEO_OUT_BATCH     32

/*
** audio output buffer (96-127)
*/
#define AUDIO_OUT_BUF       (VIDEO_OUT_BUF+VIDEO_OUT_BATCH)
#define AUDIO_OUT_BATCH     32

/*
** OGT output buffer (128-160)
*/
#define OGT_OUT_BUF     (AUDIO_OUT_BUF+AUDIO_OUT_BATCH)
#define OGT_OUT_BATCH       32

/*
**
*/
#define TEMP_DMA_RAM        (OGT_OUT_BUF+OGT_OUT_BATCH)

#define QUANT_BUF_INTRA         0
#define QUANT_BUF_NON_INTRA     64
#define QUANT_BUF_CHROMA_INTRA      128
#define QUANT_BUF_CHROMA_NON_INTRA  192

/*
** MACRO
** assert_marker_bit(b)
**
** macro to check against marker-bit.
*/
#define assert_marker_bit(b)


#define VIDEO_RESET_DELAY   1

/*
** Audio
*/
#define AUDIO_VOLUME_AMP    16  //8
/* 
** SDRAM Timing TEST // benson 2003.07.04 
*/
//#define SUPPORT_SDRAM_TEST 1
#endif/*__CONFIG_H*/