m256.h

代码有点长,需细心阅读,仅供影音视听类产品的开发人员参考

/***************************************Not Verified*************************************/


#if   CONFIG==CONFIG_COMBO_VCD
#define SDRAM_BASE_CACHED   0x88000000
#define SDRAM_BASE_UNCACHED 0xa8000000
#else
#define SDRAM_BASE_CACHED   0x40000000
#define SDRAM_BASE_UNCACHED 0xa0000000
#endif

#ifdef  TESTCHIP
    #define SDRAM_BASE      SDRAM_BASE_UNCACHED
#else
    #define SDRAM_BASE      SDRAM_BASE_CACHED
#endif

#define CVCD_MP3_OFFSET (20+45)

#define SECT_INFO          (2)
#define SECT_ENTRIES       (4)
#define QUANT_BUF_Y        (5)
#define DMARAM_BUF_Y       (5)
#define VCD_CACHE_START    (8)
#define CDROM_CACHE_START  (8)

#define DMARAM_BUF_XS       256

/*
**  CACHE LINE
*/
/******************************************************/
#define MP3SECT_CACHE_LINES 9
#define SECT_CACHE_LINES    1
/******************************************************/

/*
**  BUFFER LINE WIDTH
*/
/*************************************************************/
#define VBV_W       1024                /* VIDEO buf width  */
#define ABV_W       1024                /* AUDIO buf width  */
#define SBV_W       1024                /* SUP buf width    */
#define OBV_W       1024                /* OSD buf width    */
#define CBV_W       1024                /* DISC input buf width */

#define MP3_ABV_W 1024
/*************************************************************/
/*
** anchors
*/
/***********************************************/
#define MEM_EVBYA       (regs0->evbya)
#define MEM_EABYA       (regs0->eabya)
#define MEM_SUPYA       (regs0->supya)
#define MEM_CDYA        (regs0->cdya)
#define MEM_OSDYA       (regs0->osdya)
#define MEM_AUDYA       (regs0->audya)
#define MEM_IOPYA       (regs0->iopya)
#define MEM_REF0_LUMA   (regs0->ref0_luma)
/***********************************************/

/*
**  COMBO VCD FRAME BUFFER COMPRESS
*/
/*********************************/
#define     RF_VC_I_811     (1<<8)
#define     RF_VC_P_811     (1<<7)
#define     RF_VC_B_811     (1<<6)
#define     RF_VC_I_411     (0<<8)
#define     RF_VC_P_411     (0<<7)
#define     RF_VC_B_411     (0<<6)
#define     RF_VC_I_888     (0<<4)
#define     RF_VC_I_766     (1<<4)
#define     RF_VC_I_666     (2<<4)
#define     RF_VC_I_8655    (3<<4)
#define     RF_VC_P_888     (0<<2)
#define     RF_VC_P_766     (1<<2)
#define     RF_VC_P_666     (2<<2)
#define     RF_VC_P_8655    (3<<2)
#define     RF_VC_B_888     (0<<0)
#define     RF_VC_B_766     (1<<0)
#define     RF_VC_B_666     (2<<0)
#define     RF_VC_B_8655    (3<<0)

#define     MEM_411888      0x00
#define     MEM_411766      0x01
#define     MEM_411666      (0x02|1<<9)
#define     MEM_4118655     0x03
#define     MEM_811888      RF_VC_B_811
#define     MEM_811766      0x41
#define     MEM_811666      0x42
#define     MEM_8118655     0x43
/**************************************/

/*
**  VCD/SVCD FRAME BUFFER CONFIG
*/
/********************************************************************/
#define VIDEO_COMPRESS  MEM_411666
#define MEM_IOPYA_DEF       (VCD_CACHE_START-2)
#define MEM_AUDYA_DEF       10
#define MEM_OSDYA_DEF       37//35  //37       rbhung 2002.09.27 For "