📄 iop.h
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#ifndef __IOP_H
#define __IOP_H
#include "regmap.h"
//#include "memmap.h"
//ESP status//jhuang 2003/3/2
#define ESP_PORT 4//[ESP_PORT].5,[ESP_PORT].6,[ESP_PORT].7
//IOP control register
#define IOP_CTRL_PORT 5
//I2C device ID
#define I2C_ID_MEMORY 0xa0
#define I2C_ID_TV_ENCODE 0x40
#define I2C_ID_AUDIO_DAC 0x20
//IOP function call define
#define FUN_PORT 0
#define FUN_MASK 0xf000
#define FUN_VFD_READ (0x1<<12)
#define FUN_VFD_WRITE (0x2<<12)
#define FUN_IR_CUSTID (0x4<<12)
#define FUN_IR_GET_CUSTID (0x5<<12)
#define FUN_UART_SEND (0x6<<12)
#define FUN_I2C_WRITE (0x7<<12)
#define FUN_I2C_READ (0x8<<12)
#define FUN_GPAD_READ (0x9<<12)
//IOP IR control interface
//register mapping of RISC register
#define IR_PORT 6
//control flag
#define IR_RDY (1<<15)
#define IR_REPEAT (1<<14)
#define IrRepeatRate(x) (x<<8)
//IOP vfd control interface
//#define INIT_IOP_VFD_PARA_1 0x02
//#define INIT_IOP_VFD_PARA_2 0x8c
//#define INIT_IOP_VFD_PARA_3 0xc0
//register mapping of RISC register
#define VFD_PORT 5
//control flag
#define VFD_RDY (1<<7)
#define VFD_REPEAT (1<<6)
#define VFD_CMD 1
#define VFD_DAT0 2
#define VFD_DAT1 3
#define VFD_DAT2 4
//control flag
#define VFD_DATLEN_MASK (~0x0007)
#define VFD_DAT_LEN0 0
#define VFD_DAT_LEN1 1
#define VFD_DAT_LEN2 2
#define VFD_DAT_LEN3 3
#define VFD_DAT_LEN4 4
#define VFD_DAT_LEN5 5
#define VFD_DAT_LEN6 6
//IOP UART control interface
#define UART_DAT 1
//I2C control interface
#define I2C_CTRL_ADDR 1
#define I2C_DATA 4
#define I2C_READ_ONE (0<<5)
#define I2C_READ_CONT (1<<5)
#define I2C_RW_ERR (1<<4)
#define I2C_RD_RDY (1<<3)
//timer interface
#define TIMEOUT_10MS (1<<9)
#define TIMEOUT_1MS (1<<8)
#define IR_NORM_RECV() (regs0->iop_data[IOP_CTRL_PORT]&IR_RDY)
#define IR_REP_RECV() (regs0->iop_data[IOP_CTRL_PORT]&IR_REPEAT)
#define CLR_IR_NORM_RECV() (regs0->iop_data[IOP_CTRL_PORT]&=(~IR_RDY))
#define CLR_IR_REP_RECV() (regs0->iop_data[IOP_CTRL_PORT]&=(~IR_REPEAT))
#define VFD_NORM_RECV() (regs0->iop_data[IOP_CTRL_PORT]&VFD_RDY)
#define VFD_REP_RECV() (regs0->iop_data[IOP_CTRL_PORT]&VFD_REPEAT)
#define CLR_VFD_NORM_RECV() (regs0->iop_data[IOP_CTRL_PORT]&=(~VFD_RDY))
#define CLR_VFD_REP_RECV() (regs0->iop_data[IOP_CTRL_PORT]&=(~VFD_REPEAT))
#define TimeUp_10MS() (regs0->iop_data[IOP_CTRL_PORT]&TIMEOUT_10MS)
#define TimeUp_1MS() (regs0->iop_data[IOP_CTRL_PORT]&TIMEOUT_1MS)
#define Clr_Timer_10MS() (regs0->iop_data[IOP_CTRL_PORT]&=(~TIMEOUT_10MS))
#define Clr_Timer_1MS() (regs0->iop_data[IOP_CTRL_PORT]&=(~TIMEOUT_1MS))
#define GET_IR_KEY() (regs0->iop_data[IR_PORT]&0x00ff)
#define GET_IR_CUSTID() ((regs0->iop_data[IR_PORT]>>8)&0x00ff)
#define GET_VFD_KEY() (regs0->iop_data[VFD_PORT]&0x003f)
#define IsESP_SHOCK_READY() ( (regs0->iop_data[ESP_PORT] & (3 << 6)) == (1 << 7) )//[4].7==H [4].6==L
#define ESP_SHOCK_CLR() (regs0->iop_data[ESP_PORT] &= (~(1 << 7)))//[4].7=L
#define ESP_SHOCK_PROCESS_SET() (regs0->iop_data[ESP_PORT] |= (1 << 6) )//[4].6=H
#define ESP_SHOCK_PROCESS_CLR() ( regs0->iop_data[ESP_PORT] &= (~(1 << 6)) )//[4].6=L
#define IsESP_SHOCK_PROCESS_SET() ( regs0->iop_data[ESP_PORT] & (1 << 6) )//[4].6==H
#define ESP_SHOCK_GOTO_SET() (regs0->iop_data[ESP_PORT] &= (~(1 << 5)))//[4].5=L
#define ESP_SHOCK_GOTO_OK() (regs0->iop_data[ESP_PORT] |= (1 << 5))//[4].5=H
#define IsESP_SHOCK_GOTO_OK() (regs0->iop_data[ESP_PORT] & (1 << 5))//[4].5==H
//regs0->iop_data[4] & )
#endif /*__IOP_H */
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