iop.c

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//
// FILE
// iop.c
//
#include "config.h"
#include "regmap.h"
#include "global.h"
#include "dma.h"
#include "memmap.h"
#include "set.h"
void iop_init(const BYTE * rom, int len)
{
	int     i;
	UINT32 *p, *q;

	regs0->gpio_sel |= ((1 << 8));	//disable rom A19 set to GPIO

#ifndef SUPPORT_COMBO
	regs0->gpio_sel |= ((3 << 7));	//gpio A8,A9
	regs0->gpio_sel &= (~(1 << 9));	//gpio A10
	regs0->gpio_master[0] &= (~(0x07 << 8));	//dsa used
#endif

	regs0->gpio_master[0] &= (~(0x07 << 0));	//game GPIO 0,2

#ifdef EMU_DEMO_BOARD
	regs0->gpio_master[1] &= (~(0x0f << 6));	//vfd and ir GPIO 22,23,24,25
	//kevinlu 2001.11.27
#else
	#ifdef BBK
	regs0->gpio_master[1] &= (~(0x013 << 5));	//IOP controlled ir:GPIO25 ; I2C CLK/DATA:GPIO21,22
	#else
	regs0->gpio_master[1] &= (~(0x017 << 5));	//vfd and ir GPIO 21,22,23,25
	#endif
#endif

#ifdef SUPPORT_ESP
	regs0->gpio_master[2] &= (~(1 << 8));
#endif

	// audio clk divided from GPIO 40
	//regs0->pos_cfg = 0x08;
	//regs0->gpio_oe[2] &= (~(0x0100));
	//regs0->gpio_master[2] |= (0x100);

	regs0->iop_control = -1;			//RF_DSP24_RESET | RF_DSP24_STALL;

	p = (UINT32 *) rom;
	q = (UINT32 *) (SDRAM_BASE + regs0->iopya * 1024);
	len = (len + 3) & ~0x03;
	for(i = 0; i < len / 4; i++)
		*q++ = *p++;
	//MIPS_flush_LBC_cache();
	regs0->iop_control = 0;
}