📄 psocgpioint.lis
字号:
0000 ;
0000 ; adcinc12_asm_examplePinINT.asm
0000 ;
0000 ; Data: 29 October, 2001
0000 ; Copyright Cypress MicroSystems 2001
0000 ;
0000 ; This file is generated by the Device Editor on Application Generation.
0000 ; It contains the function that services the GPIO interrupt.
0000 ;
0000 ; Edits to this file will be preserved.
0000 ;
0006 Out8_Bypass_ADDR: equ 6h
0004 Out8_Data_ADDR: equ 4h
0104 Out8_DriveMode_0_ADDR: equ 104h
0105 Out8_DriveMode_1_ADDR: equ 105h
0106 Out8_IntCtrl_0_ADDR: equ 106h
0107 Out8_IntCtrl_1_ADDR: equ 107h
0005 Out8_IntEn_ADDR: equ 5h
0001 Out8_MASK: equ 1h
0000 ; Out0 address and mask equates
0002 Out0_Bypass_ADDR: equ 2h
0000 Out0_Data_ADDR: equ 0h
0100 Out0_DriveMode_0_ADDR: equ 100h
0101 Out0_DriveMode_1_ADDR: equ 101h
0102 Out0_IntCtrl_0_ADDR: equ 102h
0103 Out0_IntCtrl_1_ADDR: equ 103h
0001 Out0_IntEn_ADDR: equ 1h
0001 Out0_MASK: equ 1h
0000 ; Out1 address and mask equates
0002 Out1_Bypass_ADDR: equ 2h
0000 Out1_Data_ADDR: equ 0h
0100 Out1_DriveMode_0_ADDR: equ 100h
0101 Out1_DriveMode_1_ADDR: equ 101h
0102 Out1_IntCtrl_0_ADDR: equ 102h
0103 Out1_IntCtrl_1_ADDR: equ 103h
0001 Out1_IntEn_ADDR: equ 1h
0002 Out1_MASK: equ 2h
0000 ; Out2 address and mask equates
0002 Out2_Bypass_ADDR: equ 2h
0000 Out2_Data_ADDR: equ 0h
0100 Out2_DriveMode_0_ADDR: equ 100h
0101 Out2_DriveMode_1_ADDR: equ 101h
0102 Out2_IntCtrl_0_ADDR: equ 102h
0103 Out2_IntCtrl_1_ADDR: equ 103h
0001 Out2_IntEn_ADDR: equ 1h
0004 Out2_MASK: equ 4h
0000 ; Out3 address and mask equates
0002 Out3_Bypass_ADDR: equ 2h
0000 Out3_Data_ADDR: equ 0h
0100 Out3_DriveMode_0_ADDR: equ 100h
0101 Out3_DriveMode_1_ADDR: equ 101h
0102 Out3_IntCtrl_0_ADDR: equ 102h
0103 Out3_IntCtrl_1_ADDR: equ 103h
0001 Out3_IntEn_ADDR: equ 1h
0008 Out3_MASK: equ 8h
0000 ; Out4 address and mask equates
0002 Out4_Bypass_ADDR: equ 2h
0000 Out4_Data_ADDR: equ 0h
0100 Out4_DriveMode_0_ADDR: equ 100h
0101 Out4_DriveMode_1_ADDR: equ 101h
0102 Out4_IntCtrl_0_ADDR: equ 102h
0103 Out4_IntCtrl_1_ADDR: equ 103h
0001 Out4_IntEn_ADDR: equ 1h
0010 Out4_MASK: equ 10h
0000 ; Out5 address and mask equates
0002 Out5_Bypass_ADDR: equ 2h
0000 Out5_Data_ADDR: equ 0h
0100 Out5_DriveMode_0_ADDR: equ 100h
0101 Out5_DriveMode_1_ADDR: equ 101h
0102 Out5_IntCtrl_0_ADDR: equ 102h
0103 Out5_IntCtrl_1_ADDR: equ 103h
0001 Out5_IntEn_ADDR: equ 1h
0020 Out5_MASK: equ 20h
0000 ; Out6 address and mask equates
0002 Out6_Bypass_ADDR: equ 2h
0000 Out6_Data_ADDR: equ 0h
0100 Out6_DriveMode_0_ADDR: equ 100h
0101 Out6_DriveMode_1_ADDR: equ 101h
0102 Out6_IntCtrl_0_ADDR: equ 102h
0103 Out6_IntCtrl_1_ADDR: equ 103h
0001 Out6_IntEn_ADDR: equ 1h
0040 Out6_MASK: equ 40h
0000 ; Out7 address and mask equates
0002 Out7_Bypass_ADDR: equ 2h
0000 Out7_Data_ADDR: equ 0h
0100 Out7_DriveMode_0_ADDR: equ 100h
0101 Out7_DriveMode_1_ADDR: equ 101h
0102 Out7_IntCtrl_0_ADDR: equ 102h
0103 Out7_IntCtrl_1_ADDR: equ 103h
0001 Out7_IntEn_ADDR: equ 1h
0080 Out7_MASK: equ 80h
0000 ; Out9 address and mask equates
0006 Out9_Bypass_ADDR: equ 6h
0004 Out9_Data_ADDR: equ 4h
0104 Out9_DriveMode_0_ADDR: equ 104h
0105 Out9_DriveMode_1_ADDR: equ 105h
0106 Out9_IntCtrl_0_ADDR: equ 106h
0107 Out9_IntCtrl_1_ADDR: equ 107h
0005 Out9_IntEn_ADDR: equ 5h
0002 Out9_MASK: equ 2h
0000 ; Out10 address and mask equates
0006 Out10_Bypass_ADDR: equ 6h
0004 Out10_Data_ADDR: equ 4h
0104 Out10_DriveMode_0_ADDR: equ 104h
0105 Out10_DriveMode_1_ADDR: equ 105h
0106 Out10_IntCtrl_0_ADDR: equ 106h
0107 Out10_IntCtrl_1_ADDR: equ 107h
0005 Out10_IntEn_ADDR: equ 5h
0004 Out10_MASK: equ 4h
0000 ; Out11 address and mask equates
0006 Out11_Bypass_ADDR: equ 6h
0004 Out11_Data_ADDR: equ 4h
0104 Out11_DriveMode_0_ADDR: equ 104h
0105 Out11_DriveMode_1_ADDR: equ 105h
0106 Out11_IntCtrl_0_ADDR: equ 106h
0107 Out11_IntCtrl_1_ADDR: equ 107h
0005 Out11_IntEn_ADDR: equ 5h
0008 Out11_MASK: equ 8h
0000 ; Out12 address and mask equates
0006 Out12_Bypass_ADDR: equ 6h
0004 Out12_Data_ADDR: equ 4h
0104 Out12_DriveMode_0_ADDR: equ 104h
0105 Out12_DriveMode_1_ADDR: equ 105h
0106 Out12_IntCtrl_0_ADDR: equ 106h
0107 Out12_IntCtrl_1_ADDR: equ 107h
0005 Out12_IntEn_ADDR: equ 5h
0010 Out12_MASK: equ 10h
0000 ; Out13 address and mask equates
0006 Out13_Bypass_ADDR: equ 6h
0004 Out13_Data_ADDR: equ 4h
0104 Out13_DriveMode_0_ADDR: equ 104h
0105 Out13_DriveMode_1_ADDR: equ 105h
0106 Out13_IntCtrl_0_ADDR: equ 106h
0107 Out13_IntCtrl_1_ADDR: equ 107h
0005 Out13_IntEn_ADDR: equ 5h
0020 Out13_MASK: equ 20h
0000 ; Out14 address and mask equates
0006 Out14_Bypass_ADDR: equ 6h
0004 Out14_Data_ADDR: equ 4h
0104 Out14_DriveMode_0_ADDR: equ 104h
0105 Out14_DriveMode_1_ADDR: equ 105h
0106 Out14_IntCtrl_0_ADDR: equ 106h
0107 Out14_IntCtrl_1_ADDR: equ 107h
0005 Out14_IntEn_ADDR: equ 5h
0040 Out14_MASK: equ 40h
0000 ; Out15 address and mask equates
0006 Out15_Bypass_ADDR: equ 6h
0004 Out15_Data_ADDR: equ 4h
0104 Out15_DriveMode_0_ADDR: equ 104h
0105 Out15_DriveMode_1_ADDR: equ 105h
0106 Out15_IntCtrl_0_ADDR: equ 106h
0107 Out15_IntCtrl_1_ADDR: equ 107h
0005 Out15_IntEn_ADDR: equ 5h
0080 Out15_MASK: equ 80h
0000 ; Input address and mask equates
000A Input_Bypass_ADDR: equ ah
0008 Input_Data_ADDR: equ 8h
0108 Input_DriveMode_0_ADDR: equ 108h
0109 Input_DriveMode_1_ADDR: equ 109h
010A Input_IntCtrl_0_ADDR: equ 10ah
010B Input_IntCtrl_1_ADDR: equ 10bh
0009 Input_IntEn_ADDR: equ 9h
0002 Input_MASK: equ 2h
0000
export adcinc12_asm_example_GPIO_ISR
0000 adcinc12_asm_example_GPIO_ISR:
0000
0000 7E reti
0001
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