📄 adcinc12_1.lis
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0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0001 LowByte: equ 1
0000 HighByte: equ 0
0000
0000
0000 ;;------------------------------------------------------------------
0000 ;; Start:
0000 ;; SetPower:
0000 ;; Applies power setting to the module's analog PSoc block.
0000 ;; INPUTS: A contains the power setting
0000 ;; OUTPUTS: None.
0000 ;;------------------------------------------------------------------
0000 ADCINC12_1_Start:
0000 _ADCINC12_1_Start:
0000 ADCINC12_1_SetPower:
0000 _ADCINC12_1_SetPower:
0000 10 push X ;save X
0001 4F mov X,SP ;X will point at next pushed value
0002 2103 and A,03h
0004 08 push A ;X points at copy of A
0005 5D93 mov A,reg[ADCINC12_1_AtoDcr3]
0007 21FC and A,~03h ;clear power bits
0009 2B00 or A,[ X ]
000B 6093 mov reg[ADCINC12_1_AtoDcr3],A
000D 18 pop A
000E 20 pop X
000F 7F ret
0010
0010 ;;------------------------------------------------------------------
0010 ;; Stop:
0010 ;; SetPower:
0010 ;; Removes power from the module's analog PSoc block.
0010 ;; INPUTS: None.
0010 ;; OUTPUTS: None.
0010 ;;------------------------------------------------------------------
0010 ADCINC12_1_Stop:
0010 _ADCINC12_1_Stop:
0010 4193FC and reg[ADCINC12_1_AtoDcr3], ~03h
0013 7F ret
0014
0014 ;;------------------------------------------------------------------
0014 ;; Get_Samples:
0014 ;; SetPower:
0014 ;; Starts the A/D convertor and will place data is memory. A flag
0014 ;; is set whenever a new data value is available.
0014 ;; INPUTS: A passes the number of samples (0 is continous).
0014 ;; OUTPUTS: None.
0014 ;;------------------------------------------------------------------
0014 ADCINC12_1_GetSamples:
0014 _ADCINC12_1_GetSamples:
0014 5300 mov [ADCINC12_1_bIncrC],A ;number of samples
0016 43E103 or reg[INT_MSK1],(ADCINC12_1_TimerMask | ADCINC12_1_CounterMask )
0019 ;Enable both interrupts
0019 550001 mov [ADCINC12_1_cTimerU],1 ;Force the Timer to do one cycle of rest
IF ADCINC12_1_NoAZ
001C 439220 or reg[ADCINC12_1_AtoDcr2],20h ;force the Integrator into reset
ENDIF
001F 439310 or reg[ADCINC12_1_AtoDcr3],10h
0022 5500E0 mov [ADCINC12_1_cCounterU],(-(1<<(ADCINC12_1_NUMBITS - 7)));Initialize Counter
0025 6221FF mov reg[ADCINC12_1_TimerDR1],ffh
0028 6225FF mov reg[ADCINC12_1_CounterDR1],ffh
002B 622301 mov reg[ADCINC12_1_TimerCR0],01h ;enable the Timer
002E 550000 mov [ADCINC12_1_fIncr],00h ;A/D Data Ready Flag is reset
0031 7F ret
0032
0032 ;;------------------------------------------------------------------
0032 ;; StopAD:
0032 ;; Completely shuts down the A/D is an orderly manner. Both the
0032 ;; Timer and COunter interrupts are disabled.
0032 ;; INPUTS: None.
0032 ;; OUTPUTS: None.
0032 ;;------------------------------------------------------------------
0032 ADCINC12_1_StopAD:
0032 _ADCINC12_1_StopAD:
0032 622300 mov reg[ADCINC12_1_TimerCR0],00h ;disable the Timer
0035 622700 mov reg[ADCINC12_1_CounterCR0],00h ;disable the Counter
0038 40 nop
0039 40 nop
003A ;Disable both interrupts
if DISABLE_INT_FIX
003A 5DFF mov A, reg[CPU_SCR] ; save the current Global interrupt state
003C 70FE and F, ~FlagGlobalIE
endif
003E 41E1FC and reg[INT_MSK1], ~(ADCINC12_1_TimerMask | ADCINC12_1_CounterMask ) ; disable specified interrupt enable bit
if DISABLE_INT_FIX
0041 2180 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0043 A003 jz . + 4 ; jump if global interrupt disabled
0045 7101 or F, FlagGlobalIE
endif
IF ADCINC12_1_NoAZ
0047 439220 or reg[ADCINC12_1_AtoDcr2],20h ;reset Integrator
ENDIF
004A 439310 or reg[ADCINC12_1_AtoDcr3],10h
004D 7F ret
004E ;;------------------------------------------------------------------
004E ;; fIsData:
004E ;; Returns the status of the A/D Data
004E ;; is set whenever a new data value is available.
004E ;; INPUTS: None.
004E ;; OUTPUTS: A returned data status A =: 0 no data available
004E ;; !=: 0 data available.
004E ;;------------------------------------------------------------------
004E ADCINC12_1_fIsData:
004E _ADCINC12_1_fIsData:
004E 5100 mov A,[ADCINC12_1_fIncr]
0050 7F ret
0051
0051 ;;------------------------------------------------------------------
0051 ;; iGetData:
0051 ;; Returns the data from the A/D. Does not check if data is
0051 ;; available.
0051 ;; is set whenever a new data value is available.
0051 ;; INPUTS: None.
0051 ;; OUTPUTS: X:A returns the A/D data value.
0051 ;;------------------------------------------------------------------
0051 ADCINC12_1_iGetData:
0051 _ADCINC12_1_iGetData:
0051 5800 mov X,[(ADCINC12_1_iIncr + HighByte)]
0053 5101 mov A,[(ADCINC12_1_iIncr + LowByte)]
0055 7F ret
0056
0056 ;;------------------------------------------------------------------
0056 ;; ClearFlag:
0056 ;; clears the data ready flag.
0056 ;; INPUTS: None.
0056 ;; OUTPUTS: None.
0056 ;;------------------------------------------------------------------
0056 ADCINC12_1_ClearFlag:
0056 _ADCINC12_1_ClearFlag:
0056 550000 mov [ADCINC12_1_fIncr],00h
0059 7F ret
005A
005A ADCINC12_1_API_End:
005A
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