📄 adcinc12_1int.lis
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0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0000 macro Suspend_CodeCompressor
0000 or f, 0
0000 macro Resume_CodeCompressor
0000 add sp, 0
export ADCINC12_1_CNT_INT
export ADCINC12_1_TMR_INT
export ADCINC12_1_cTimerU
export ADCINC12_1_cCounterU
export _ADCINC12_1_iIncr
export ADCINC12_1_iIncr
export _ADCINC12_1_fIncr
export ADCINC12_1_fIncr
export ADCINC12_1_bIncrC
area bss(RAM)
0000 ADCINC12_1_cTimerU: BLK 1 ;The Upper byte of the Timer
0001 ADCINC12_1_cCounterU: BLK 1 ;The Upper byte of the Counter
0002 _ADCINC12_1_iIncr:
0002 ADCINC12_1_iIncr: BLK 2 ;A/D value
0004 _ADCINC12_1_fIncr:
0004 ADCINC12_1_fIncr: BLK 1 ;Data Valid Flag
0005 ADCINC12_1_bIncrC: BLK 1 ;# of times to run A/D
0006
area text(ROM,REL)
0001 LowByte: equ 1
0000 HighByte: equ 0
0000
0000 ;;------------------------------------------------------------------
0000 ;; CNT_INT:
0000 ;; Increment the upper (software) half on the counter whenever the
0000 ;; lower (hardware) half of the counter underflows.
0000 ;; INPUTS: None.
0000 ;; OUTPUTS: None.
0000 ;;------------------------------------------------------------------
0000 ADCINC12_1_CNT_INT:
0000 7601 inc [ADCINC12_1_cCounterU]
0002 7E reti
0003
0003 ;;------------------------------------------------------------------
0003 ;; TMR_INT:
0003 ;; This routine allows the counter to collect data for 64 timer cycles
0003 ;; This routine then holds the integrater in reset for one cycle while
0003 ;; the A/D value is calculated.
0003 ;; INPUTS: None.
0003 ;; OUTPUTS: None.
0003 ;;------------------------------------------------------------------
0003 ADCINC12_1_TMR_INT:
0003 7A00 dec [ADCINC12_1_cTimerU]
0005 ; if(upper count >0 )
0005 A002 jz else1
0007 7E reti
0008 else1:;(upper count decremented to 0)
0008 499310 tst reg[ADCINC12_1_AtoDcr3],10h
000B A00F jz else2
000D ; if(A/D has been in reset mode)
000D 40 nop ; Dummy statement to keep time
000E ; between turning on and off counter
000E ; the same.
000E 622701 mov reg[ADCINC12_1_CounterCR0],01h ; Enable Counter
0011 4193EF and reg[ADCINC12_1_AtoDcr3],~10h ; Enable Analog Integrator
IF ADCINC12_1_NoAZ
0014 4192DF and reg[ADCINC12_1_AtoDcr2],~20h
ENDIF
0017 550040 mov [ADCINC12_1_cTimerU],(1<<(ADCINC12_1_NUMBITS - 6))
001A ; This will be the real counter value
001A 7E reti
001B else2:;(A/D has been in integrate mode)
001B 7110 or F, FlagXIOMask
001D 41250F and reg[ADCINC12_1_CounterSL], 0x0F ; Disable input to counter
0020 70EF and F, ~FlagXIOMask
0022
0022 7101 or F,01h ;Enable the interrupts
0024 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0024 ; Good place to add code to switch inputs for multiplexed input to ADC
0024 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IF ADCINC12_1_NoAZ
0024 439220 or reg[ADCINC12_1_AtoDcr2],20h ;Reset Integrator
ENDIF
0027 439310 or reg[ADCINC12_1_AtoDcr3],10h
002A 08 push A
002B 5D24 mov A, reg[ADCINC12_1_CounterDR0] ;read Counter
002D 5D26 mov A, reg[ADCINC12_1_CounterDR2] ;now you really read the data
002F
002F 622700 mov reg[ADCINC12_1_CounterCR0],00h ;disable counter
0032 7110 or F, FlagXIOMask
0034 432540 or reg[ADCINC12_1_CounterSL],ADCINC12_1_CNTINPUT ; Reconnect counter to comparitor
0037 70EF and F, ~FlagXIOMask
0039
0039
0039 73 cpl A
003A 3C0120 cmp [ADCINC12_1_cCounterU],(1<<(ADCINC12_1_NUMBITS - 7))
003D B005 jnz endif10
003F ; if(max positive value)
003F 7A01 dec [ADCINC12_1_cCounterU]
0041 50FF mov A,ffh
0043 endif10:
0043 6801 asr [ADCINC12_1_cCounterU] ; divide by 4
0045 6D rrc A
0046 6801 asr [ADCINC12_1_cCounterU]
0048 6D rrc A
0049 ;
0049 5F0201 mov [(ADCINC12_1_iIncr + HighByte)],[ADCINC12_1_cCounterU]
004C 5303 mov [(ADCINC12_1_iIncr + LowByte)],A
004E 550401 mov [ADCINC12_1_fIncr],01h ;Set AD data flag
0051 18 pop A
0052 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0052 ; User code here for interrupt system.
0052 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
0052 3C0500 cmp [ADCINC12_1_bIncrC],00h
0055 A017 jz endif3
0057 ; if(ADCINC12_1_bIncrC is not zero)
0057 7A05 dec [ADCINC12_1_bIncrC]
0059 B013 jnz endif4
005B ; if(ADCINC12_1_bIncrC has decremented down to zero to 0)
005B 622300 mov reg[ADCINC12_1_TimerCR0],00h ;disable the Timer
005E 622700 mov reg[ADCINC12_1_CounterCR0],00h ;disable the Counter
0061 40 nop
0062 40 nop
0063 41E1FC and reg[INT_MSK1],~(ADCINC12_1_TimerMask | ADCINC12_1_CounterMask)
0066 ;Disable both interrupts
IF ADCINC12_1_NoAZ
0066 439220 or reg[ADCINC12_1_AtoDcr2],20h ;Reset Integrator
ENDIF
0069 439310 or reg[ADCINC12_1_AtoDcr3],10h
006C 7E reti
006D endif4:;
006D endif3:;
006D endif2:;
006D 550001 mov [ADCINC12_1_cTimerU],1 ;Set Timer for one cycle of reset
0070 5501E0 mov [ADCINC12_1_cCounterU],(-(1<<(ADCINC12_1_NUMBITS - 7))) ;Set Counter hardware for easy enable
0073 6225FF mov reg[ADCINC12_1_CounterDR1],ffh
0076 7E reti
0077 endif1:;
0077
0077 ADCINC12_1_APIINT_END:
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