psocgpioint.h

Application Note Abstract The unique configuration of the PSoC&reg switched capacitor blocks allows

// x0 address and mask defines
#pragma	ioport	x0_Bypass_ADDR:	0x2
BYTE			x0_Bypass_ADDR;
#pragma	ioport	x0_Data_ADDR:	0x0
BYTE			x0_Data_ADDR;
#pragma	ioport	x0_DriveMode_0_ADDR:	0x100
BYTE			x0_DriveMode_0_ADDR;
#pragma	ioport	x0_DriveMode_1_ADDR:	0x101
BYTE			x0_DriveMode_1_ADDR;
#pragma	ioport	x0_IntCtrl_0_ADDR:	0x102
BYTE			x0_IntCtrl_0_ADDR;
#pragma	ioport	x0_IntCtrl_1_ADDR:	0x103
BYTE			x0_IntCtrl_1_ADDR;
#pragma	ioport	x0_IntEn_ADDR:	0x1
BYTE			x0_IntEn_ADDR;
#define x0_MASK 0x1
// x1 address and mask defines
#pragma	ioport	x1_Bypass_ADDR:	0x2
BYTE			x1_Bypass_ADDR;
#pragma	ioport	x1_Data_ADDR:	0x0
BYTE			x1_Data_ADDR;
#pragma	ioport	x1_DriveMode_0_ADDR:	0x100
BYTE			x1_DriveMode_0_ADDR;
#pragma	ioport	x1_DriveMode_1_ADDR:	0x101
BYTE			x1_DriveMode_1_ADDR;
#pragma	ioport	x1_IntCtrl_0_ADDR:	0x102
BYTE			x1_IntCtrl_0_ADDR;
#pragma	ioport	x1_IntCtrl_1_ADDR:	0x103
BYTE			x1_IntCtrl_1_ADDR;
#pragma	ioport	x1_IntEn_ADDR:	0x1
BYTE			x1_IntEn_ADDR;
#define x1_MASK 0x2
// Vload2 address and mask defines
#pragma	ioport	Vload2_Bypass_ADDR:	0x2
BYTE			Vload2_Bypass_ADDR;
#pragma	ioport	Vload2_Data_ADDR:	0x0
BYTE			Vload2_Data_ADDR;
#pragma	ioport	Vload2_DriveMode_0_ADDR:	0x100
BYTE			Vload2_DriveMode_0_ADDR;
#pragma	ioport	Vload2_DriveMode_1_ADDR:	0x101
BYTE			Vload2_DriveMode_1_ADDR;
#pragma	ioport	Vload2_IntCtrl_0_ADDR:	0x102
BYTE			Vload2_IntCtrl_0_ADDR;
#pragma	ioport	Vload2_IntCtrl_1_ADDR:	0x103
BYTE			Vload2_IntCtrl_1_ADDR;
#pragma	ioport	Vload2_IntEn_ADDR:	0x1
BYTE			Vload2_IntEn_ADDR;
#define Vload2_MASK 0x4
// Vout1 address and mask defines
#pragma	ioport	Vout1_Bypass_ADDR:	0x2
BYTE			Vout1_Bypass_ADDR;
#pragma	ioport	Vout1_Data_ADDR:	0x0
BYTE			Vout1_Data_ADDR;
#pragma	ioport	Vout1_DriveMode_0_ADDR:	0x100
BYTE			Vout1_DriveMode_0_ADDR;
#pragma	ioport	Vout1_DriveMode_1_ADDR:	0x101
BYTE			Vout1_DriveMode_1_ADDR;
#pragma	ioport	Vout1_IntCtrl_0_ADDR:	0x102
BYTE			Vout1_IntCtrl_0_ADDR;
#pragma	ioport	Vout1_IntCtrl_1_ADDR:	0x103
BYTE			Vout1_IntCtrl_1_ADDR;
#pragma	ioport	Vout1_IntEn_ADDR:	0x1
BYTE			Vout1_IntEn_ADDR;
#define Vout1_MASK 0x8
// Vout2 address and mask defines
#pragma	ioport	Vout2_Bypass_ADDR:	0x2
BYTE			Vout2_Bypass_ADDR;
#pragma	ioport	Vout2_Data_ADDR:	0x0
BYTE			Vout2_Data_ADDR;
#pragma	ioport	Vout2_DriveMode_0_ADDR:	0x100
BYTE			Vout2_DriveMode_0_ADDR;
#pragma	ioport	Vout2_DriveMode_1_ADDR:	0x101
BYTE			Vout2_DriveMode_1_ADDR;
#pragma	ioport	Vout2_IntCtrl_0_ADDR:	0x102
BYTE			Vout2_IntCtrl_0_ADDR;
#pragma	ioport	Vout2_IntCtrl_1_ADDR:	0x103
BYTE			Vout2_IntCtrl_1_ADDR;
#pragma	ioport	Vout2_IntEn_ADDR:	0x1
BYTE			Vout2_IntEn_ADDR;
#define Vout2_MASK 0x10
// x5 address and mask defines
#pragma	ioport	x5_Bypass_ADDR:	0x2
BYTE			x5_Bypass_ADDR;
#pragma	ioport	x5_Data_ADDR:	0x0
BYTE			x5_Data_ADDR;
#pragma	ioport	x5_DriveMode_0_ADDR:	0x100
BYTE			x5_DriveMode_0_ADDR;
#pragma	ioport	x5_DriveMode_1_ADDR:	0x101
BYTE			x5_DriveMode_1_ADDR;
#pragma	ioport	x5_IntCtrl_0_ADDR:	0x102
BYTE			x5_IntCtrl_0_ADDR;
#pragma	ioport	x5_IntCtrl_1_ADDR:	0x103
BYTE			x5_IntCtrl_1_ADDR;
#pragma	ioport	x5_IntEn_ADDR:	0x1
BYTE			x5_IntEn_ADDR;
#define x5_MASK 0x20
// x6 address and mask defines
#pragma	ioport	x6_Bypass_ADDR:	0x2
BYTE			x6_Bypass_ADDR;
#pragma	ioport	x6_Data_ADDR:	0x0
BYTE			x6_Data_ADDR;
#pragma	ioport	x6_DriveMode_0_ADDR:	0x100
BYTE			x6_DriveMode_0_ADDR;
#pragma	ioport	x6_DriveMode_1_ADDR:	0x101
BYTE			x6_DriveMode_1_ADDR;
#pragma	ioport	x6_IntCtrl_0_ADDR:	0x102
BYTE			x6_IntCtrl_0_ADDR;
#pragma	ioport	x6_IntCtrl_1_ADDR:	0x103
BYTE			x6_IntCtrl_1_ADDR;
#pragma	ioport	x6_IntEn_ADDR:	0x1
BYTE			x6_IntEn_ADDR;
#define x6_MASK 0x40
// x7 address and mask defines
#pragma	ioport	x7_Bypass_ADDR:	0x2
BYTE			x7_Bypass_ADDR;
#pragma	ioport	x7_Data_ADDR:	0x0
BYTE			x7_Data_ADDR;
#pragma	ioport	x7_DriveMode_0_ADDR:	0x100
BYTE			x7_DriveMode_0_ADDR;
#pragma	ioport	x7_DriveMode_1_ADDR:	0x101
BYTE			x7_DriveMode_1_ADDR;
#pragma	ioport	x7_IntCtrl_0_ADDR:	0x102
BYTE			x7_IntCtrl_0_ADDR;
#pragma	ioport	x7_IntCtrl_1_ADDR:	0x103
BYTE			x7_IntCtrl_1_ADDR;
#pragma	ioport	x7_IntEn_ADDR:	0x1
BYTE			x7_IntEn_ADDR;
#define x7_MASK 0x80
// y0 address and mask defines
#pragma	ioport	y0_Bypass_ADDR:	0x6
BYTE			y0_Bypass_ADDR;
#pragma	ioport	y0_Data_ADDR:	0x4
BYTE			y0_Data_ADDR;
#pragma	ioport	y0_DriveMode_0_ADDR:	0x104
BYTE			y0_DriveMode_0_ADDR;
#pragma	ioport	y0_DriveMode_1_ADDR:	0x105
BYTE			y0_DriveMode_1_ADDR;
#pragma	ioport	y0_IntCtrl_0_ADDR:	0x106
BYTE			y0_IntCtrl_0_ADDR;
#pragma	ioport	y0_IntCtrl_1_ADDR:	0x107
BYTE			y0_IntCtrl_1_ADDR;
#pragma	ioport	y0_IntEn_ADDR:	0x5
BYTE			y0_IntEn_ADDR;
#define y0_MASK 0x1
// y1 address and mask defines
#pragma	ioport	y1_Bypass_ADDR:	0x6
BYTE			y1_Bypass_ADDR;
#pragma	ioport	y1_Data_ADDR:	0x4
BYTE			y1_Data_ADDR;
#pragma	ioport	y1_DriveMode_0_ADDR:	0x104
BYTE			y1_DriveMode_0_ADDR;
#pragma	ioport	y1_DriveMode_1_ADDR:	0x105
BYTE			y1_DriveMode_1_ADDR;
#pragma	ioport	y1_IntCtrl_0_ADDR:	0x106
BYTE			y1_IntCtrl_0_ADDR;
#pragma	ioport	y1_IntCtrl_1_ADDR:	0x107
BYTE			y1_IntCtrl_1_ADDR;
#pragma	ioport	y1_IntEn_ADDR:	0x5
BYTE			y1_IntEn_ADDR;
#define y1_MASK 0x2
// y2 address and mask defines
#pragma	ioport	y2_Bypass_ADDR:	0x6
BYTE			y2_Bypass_ADDR;
#pragma	ioport	y2_Data_ADDR:	0x4
BYTE			y2_Data_ADDR;
#pragma	ioport	y2_DriveMode_0_ADDR:	0x104
BYTE			y2_DriveMode_0_ADDR;
#pragma	ioport	y2_DriveMode_1_ADDR:	0x105
BYTE			y2_DriveMode_1_ADDR;
#pragma	ioport	y2_IntCtrl_0_ADDR:	0x106
BYTE			y2_IntCtrl_0_ADDR;
#pragma	ioport	y2_IntCtrl_1_ADDR:	0x107
BYTE			y2_IntCtrl_1_ADDR;
#pragma	ioport	y2_IntEn_ADDR:	0x5
BYTE			y2_IntEn_ADDR;
#define y2_MASK 0x4
// y3 address and mask defines
#pragma	ioport	y3_Bypass_ADDR:	0x6
BYTE			y3_Bypass_ADDR;
#pragma	ioport	y3_Data_ADDR:	0x4
BYTE			y3_Data_ADDR;
#pragma	ioport	y3_DriveMode_0_ADDR:	0x104
BYTE			y3_DriveMode_0_ADDR;
#pragma	ioport	y3_DriveMode_1_ADDR:	0x105
BYTE			y3_DriveMode_1_ADDR;
#pragma	ioport	y3_IntCtrl_0_ADDR:	0x106
BYTE			y3_IntCtrl_0_ADDR;
#pragma	ioport	y3_IntCtrl_1_ADDR:	0x107
BYTE			y3_IntCtrl_1_ADDR;
#pragma	ioport	y3_IntEn_ADDR:	0x5
BYTE			y3_IntEn_ADDR;
#define y3_MASK 0x8
// y4 address and mask defines
#pragma	ioport	y4_Bypass_ADDR:	0x6
BYTE			y4_Bypass_ADDR;
#pragma	ioport	y4_Data_ADDR:	0x4
BYTE			y4_Data_ADDR;
#pragma	ioport	y4_DriveMode_0_ADDR:	0x104
BYTE			y4_DriveMode_0_ADDR;
#pragma	ioport	y4_DriveMode_1_ADDR:	0x105
BYTE			y4_DriveMode_1_ADDR;
#pragma	ioport	y4_IntCtrl_0_ADDR:	0x106
BYTE			y4_IntCtrl_0_ADDR;
#pragma	ioport	y4_IntCtrl_1_ADDR:	0x107
BYTE			y4_IntCtrl_1_ADDR;
#pragma	ioport	y4_IntEn_ADDR:	0x5
BYTE			y4_IntEn_ADDR;
#define y4_MASK 0x10
// y5 address and mask defines
#pragma	ioport	y5_Bypass_ADDR:	0x6
BYTE			y5_Bypass_ADDR;
#pragma	ioport	y5_Data_ADDR:	0x4
BYTE			y5_Data_ADDR;
#pragma	ioport	y5_DriveMode_0_ADDR:	0x104
BYTE			y5_DriveMode_0_ADDR;
#pragma	ioport	y5_DriveMode_1_ADDR:	0x105
BYTE			y5_DriveMode_1_ADDR;
#pragma	ioport	y5_IntCtrl_0_ADDR:	0x106
BYTE			y5_IntCtrl_0_ADDR;
#pragma	ioport	y5_IntCtrl_1_ADDR:	0x107
BYTE			y5_IntCtrl_1_ADDR;
#pragma	ioport	y5_IntEn_ADDR:	0x5
BYTE			y5_IntEn_ADDR;
#define y5_MASK 0x20
// y6 address and mask defines
#pragma	ioport	y6_Bypass_ADDR:	0x6
BYTE			y6_Bypass_ADDR;
#pragma	ioport	y6_Data_ADDR:	0x4
BYTE			y6_Data_ADDR;
#pragma	ioport	y6_DriveMode_0_ADDR:	0x104
BYTE			y6_DriveMode_0_ADDR;
#pragma	ioport	y6_DriveMode_1_ADDR:	0x105
BYTE			y6_DriveMode_1_ADDR;
#pragma	ioport	y6_IntCtrl_0_ADDR:	0x106
BYTE			y6_IntCtrl_0_ADDR;
#pragma	ioport	y6_IntCtrl_1_ADDR:	0x107
BYTE			y6_IntCtrl_1_ADDR;
#pragma	ioport	y6_IntEn_ADDR:	0x5
BYTE			y6_IntEn_ADDR;
#define y6_MASK 0x40
// y7 address and mask defines
#pragma	ioport	y7_Bypass_ADDR:	0x6
BYTE			y7_Bypass_ADDR;
#pragma	ioport	y7_Data_ADDR:	0x4
BYTE			y7_Data_ADDR;
#pragma	ioport	y7_DriveMode_0_ADDR:	0x104
BYTE			y7_DriveMode_0_ADDR;
#pragma	ioport	y7_DriveMode_1_ADDR:	0x105
BYTE			y7_DriveMode_1_ADDR;
#pragma	ioport	y7_IntCtrl_0_ADDR:	0x106
BYTE			y7_IntCtrl_0_ADDR;
#pragma	ioport	y7_IntCtrl_1_ADDR:	0x107
BYTE			y7_IntCtrl_1_ADDR;
#pragma	ioport	y7_IntEn_ADDR:	0x5
BYTE			y7_IntEn_ADDR;
#define y7_MASK 0x80
// z0 address and mask defines
#pragma	ioport	z0_Bypass_ADDR:	0xa
BYTE			z0_Bypass_ADDR;
#pragma	ioport	z0_Data_ADDR:	0x8
BYTE			z0_Data_ADDR;
#pragma	ioport	z0_DriveMode_0_ADDR:	0x108
BYTE			z0_DriveMode_0_ADDR;
#pragma	ioport	z0_DriveMode_1_ADDR:	0x109
BYTE			z0_DriveMode_1_ADDR;
#pragma	ioport	z0_IntCtrl_0_ADDR:	0x10a
BYTE			z0_IntCtrl_0_ADDR;
#pragma	ioport	z0_IntCtrl_1_ADDR:	0x10b
BYTE			z0_IntCtrl_1_ADDR;
#pragma	ioport	z0_IntEn_ADDR:	0x9
BYTE			z0_IntEn_ADDR;
#define z0_MASK 0x1
// Vload1 address and mask defines
#pragma	ioport	Vload1_Bypass_ADDR:	0xa
BYTE			Vload1_Bypass_ADDR;
#pragma	ioport	Vload1_Data_ADDR:	0x8
BYTE			Vload1_Data_ADDR;
#pragma	ioport	Vload1_DriveMode_0_ADDR:	0x108
BYTE			Vload1_DriveMode_0_ADDR;
#pragma	ioport	Vload1_DriveMode_1_ADDR:	0x109
BYTE			Vload1_DriveMode_1_ADDR;
#pragma	ioport	Vload1_IntCtrl_0_ADDR:	0x10a
BYTE			Vload1_IntCtrl_0_ADDR;
#pragma	ioport	Vload1_IntCtrl_1_ADDR:	0x10b
BYTE			Vload1_IntCtrl_1_ADDR;
#pragma	ioport	Vload1_IntEn_ADDR:	0x9
BYTE			Vload1_IntEn_ADDR;
#define Vload1_MASK 0x2
// z2 address and mask defines
#pragma	ioport	z2_Bypass_ADDR:	0xa
BYTE			z2_Bypass_ADDR;
#pragma	ioport	z2_Data_ADDR:	0x8
BYTE			z2_Data_ADDR;
#pragma	ioport	z2_DriveMode_0_ADDR:	0x108
BYTE			z2_DriveMode_0_ADDR;
#pragma	ioport	z2_DriveMode_1_ADDR:	0x109
BYTE			z2_DriveMode_1_ADDR;
#pragma	ioport	z2_IntCtrl_0_ADDR:	0x10a
BYTE			z2_IntCtrl_0_ADDR;
#pragma	ioport	z2_IntCtrl_1_ADDR:	0x10b
BYTE			z2_IntCtrl_1_ADDR;
#pragma	ioport	z2_IntEn_ADDR:	0x9
BYTE			z2_IntEn_ADDR;
#define z2_MASK 0x4
// z3 address and mask defines
#pragma	ioport	z3_Bypass_ADDR:	0xa
BYTE			z3_Bypass_ADDR;
#pragma	ioport	z3_Data_ADDR:	0x8
BYTE			z3_Data_ADDR;
#pragma	ioport	z3_DriveMode_0_ADDR:	0x108
BYTE			z3_DriveMode_0_ADDR;
#pragma	ioport	z3_DriveMode_1_ADDR:	0x109
BYTE			z3_DriveMode_1_ADDR;
#pragma	ioport	z3_IntCtrl_0_ADDR:	0x10a
BYTE			z3_IntCtrl_0_ADDR;
#pragma	ioport	z3_IntCtrl_1_ADDR:	0x10b
BYTE			z3_IntCtrl_1_ADDR;
#pragma	ioport	z3_IntEn_ADDR:	0x9
BYTE			z3_IntEn_ADDR;
#define z3_MASK 0x8
// z4 address and mask defines
#pragma	ioport	z4_Bypass_ADDR:	0xa
BYTE			z4_Bypass_ADDR;
#pragma	ioport	z4_Data_ADDR:	0x8
BYTE			z4_Data_ADDR;
#pragma	ioport	z4_DriveMode_0_ADDR:	0x108
BYTE			z4_DriveMode_0_ADDR;
#pragma	ioport	z4_DriveMode_1_ADDR:	0x109
BYTE			z4_DriveMode_1_ADDR;
#pragma	ioport	z4_IntCtrl_0_ADDR:	0x10a
BYTE			z4_IntCtrl_0_ADDR;
#pragma	ioport	z4_IntCtrl_1_ADDR:	0x10b
BYTE			z4_IntCtrl_1_ADDR;
#pragma	ioport	z4_IntEn_ADDR:	0x9
BYTE			z4_IntEn_ADDR;
#define z4_MASK 0x10
// z5 address and mask defines
#pragma	ioport	z5_Bypass_ADDR:	0xa
BYTE			z5_Bypass_ADDR;
#pragma	ioport	z5_Data_ADDR:	0x8
BYTE			z5_Data_ADDR;
#pragma	ioport	z5_DriveMode_0_ADDR:	0x108
BYTE			z5_DriveMode_0_ADDR;
#pragma	ioport	z5_DriveMode_1_ADDR:	0x109
BYTE			z5_DriveMode_1_ADDR;
#pragma	ioport	z5_IntCtrl_0_ADDR:	0x10a
BYTE			z5_IntCtrl_0_ADDR;
#pragma	ioport	z5_IntCtrl_1_ADDR:	0x10b
BYTE			z5_IntCtrl_1_ADDR;
#pragma	ioport	z5_IntEn_ADDR:	0x9
BYTE			z5_IntEn_ADDR;
#define z5_MASK 0x20
// z6 address and mask defines
#pragma	ioport	z6_Bypass_ADDR:	0xa
BYTE			z6_Bypass_ADDR;
#pragma	ioport	z6_Data_ADDR:	0x8
BYTE			z6_Data_ADDR;
#pragma	ioport	z6_DriveMode_0_ADDR:	0x108
BYTE			z6_DriveMode_0_ADDR;
#pragma	ioport	z6_DriveMode_1_ADDR:	0x109
BYTE			z6_DriveMode_1_ADDR;
#pragma	ioport	z6_IntCtrl_0_ADDR:	0x10a
BYTE			z6_IntCtrl_0_ADDR;
#pragma	ioport	z6_IntCtrl_1_ADDR:	0x10b
BYTE			z6_IntCtrl_1_ADDR;
#pragma	ioport	z6_IntEn_ADDR:	0x9
BYTE			z6_IntEn_ADDR;
#define z6_MASK 0x40
// z7 address and mask defines
#pragma	ioport	z7_Bypass_ADDR:	0xa
BYTE			z7_Bypass_ADDR;
#pragma	ioport	z7_Data_ADDR:	0x8
BYTE			z7_Data_ADDR;
#pragma	ioport	z7_DriveMode_0_ADDR:	0x108
BYTE			z7_DriveMode_0_ADDR;
#pragma	ioport	z7_DriveMode_1_ADDR:	0x109
BYTE			z7_DriveMode_1_ADDR;
#pragma	ioport	z7_IntCtrl_0_ADDR:	0x10a
BYTE			z7_IntCtrl_0_ADDR;
#pragma	ioport	z7_IntCtrl_1_ADDR:	0x10b
BYTE			z7_IntCtrl_1_ADDR;
#pragma	ioport	z7_IntEn_ADDR:	0x9
BYTE			z7_IntEn_ADDR;
#define z7_MASK 0x80