psocgpioint.inc

Application Note Abstract The unique configuration of the PSoC&reg switched capacitor blocks allows

; x0 address and mask equates
x0_Bypass_ADDR:	equ	2h
x0_Data_ADDR:	equ	0h
x0_DriveMode_0_ADDR:	equ	100h
x0_DriveMode_1_ADDR:	equ	101h
x0_IntCtrl_0_ADDR:	equ	102h
x0_IntCtrl_1_ADDR:	equ	103h
x0_IntEn_ADDR:	equ	1h
x0_MASK:	equ	1h
; x1 address and mask equates
x1_Bypass_ADDR:	equ	2h
x1_Data_ADDR:	equ	0h
x1_DriveMode_0_ADDR:	equ	100h
x1_DriveMode_1_ADDR:	equ	101h
x1_IntCtrl_0_ADDR:	equ	102h
x1_IntCtrl_1_ADDR:	equ	103h
x1_IntEn_ADDR:	equ	1h
x1_MASK:	equ	2h
; Vload2 address and mask equates
Vload2_Bypass_ADDR:	equ	2h
Vload2_Data_ADDR:	equ	0h
Vload2_DriveMode_0_ADDR:	equ	100h
Vload2_DriveMode_1_ADDR:	equ	101h
Vload2_IntCtrl_0_ADDR:	equ	102h
Vload2_IntCtrl_1_ADDR:	equ	103h
Vload2_IntEn_ADDR:	equ	1h
Vload2_MASK:	equ	4h
; Vout1 address and mask equates
Vout1_Bypass_ADDR:	equ	2h
Vout1_Data_ADDR:	equ	0h
Vout1_DriveMode_0_ADDR:	equ	100h
Vout1_DriveMode_1_ADDR:	equ	101h
Vout1_IntCtrl_0_ADDR:	equ	102h
Vout1_IntCtrl_1_ADDR:	equ	103h
Vout1_IntEn_ADDR:	equ	1h
Vout1_MASK:	equ	8h
; Vout2 address and mask equates
Vout2_Bypass_ADDR:	equ	2h
Vout2_Data_ADDR:	equ	0h
Vout2_DriveMode_0_ADDR:	equ	100h
Vout2_DriveMode_1_ADDR:	equ	101h
Vout2_IntCtrl_0_ADDR:	equ	102h
Vout2_IntCtrl_1_ADDR:	equ	103h
Vout2_IntEn_ADDR:	equ	1h
Vout2_MASK:	equ	10h
; x5 address and mask equates
x5_Bypass_ADDR:	equ	2h
x5_Data_ADDR:	equ	0h
x5_DriveMode_0_ADDR:	equ	100h
x5_DriveMode_1_ADDR:	equ	101h
x5_IntCtrl_0_ADDR:	equ	102h
x5_IntCtrl_1_ADDR:	equ	103h
x5_IntEn_ADDR:	equ	1h
x5_MASK:	equ	20h
; x6 address and mask equates
x6_Bypass_ADDR:	equ	2h
x6_Data_ADDR:	equ	0h
x6_DriveMode_0_ADDR:	equ	100h
x6_DriveMode_1_ADDR:	equ	101h
x6_IntCtrl_0_ADDR:	equ	102h
x6_IntCtrl_1_ADDR:	equ	103h
x6_IntEn_ADDR:	equ	1h
x6_MASK:	equ	40h
; x7 address and mask equates
x7_Bypass_ADDR:	equ	2h
x7_Data_ADDR:	equ	0h
x7_DriveMode_0_ADDR:	equ	100h
x7_DriveMode_1_ADDR:	equ	101h
x7_IntCtrl_0_ADDR:	equ	102h
x7_IntCtrl_1_ADDR:	equ	103h
x7_IntEn_ADDR:	equ	1h
x7_MASK:	equ	80h
; y0 address and mask equates
y0_Bypass_ADDR:	equ	6h
y0_Data_ADDR:	equ	4h
y0_DriveMode_0_ADDR:	equ	104h
y0_DriveMode_1_ADDR:	equ	105h
y0_IntCtrl_0_ADDR:	equ	106h
y0_IntCtrl_1_ADDR:	equ	107h
y0_IntEn_ADDR:	equ	5h
y0_MASK:	equ	1h
; y1 address and mask equates
y1_Bypass_ADDR:	equ	6h
y1_Data_ADDR:	equ	4h
y1_DriveMode_0_ADDR:	equ	104h
y1_DriveMode_1_ADDR:	equ	105h
y1_IntCtrl_0_ADDR:	equ	106h
y1_IntCtrl_1_ADDR:	equ	107h
y1_IntEn_ADDR:	equ	5h
y1_MASK:	equ	2h
; y2 address and mask equates
y2_Bypass_ADDR:	equ	6h
y2_Data_ADDR:	equ	4h
y2_DriveMode_0_ADDR:	equ	104h
y2_DriveMode_1_ADDR:	equ	105h
y2_IntCtrl_0_ADDR:	equ	106h
y2_IntCtrl_1_ADDR:	equ	107h
y2_IntEn_ADDR:	equ	5h
y2_MASK:	equ	4h
; y3 address and mask equates
y3_Bypass_ADDR:	equ	6h
y3_Data_ADDR:	equ	4h
y3_DriveMode_0_ADDR:	equ	104h
y3_DriveMode_1_ADDR:	equ	105h
y3_IntCtrl_0_ADDR:	equ	106h
y3_IntCtrl_1_ADDR:	equ	107h
y3_IntEn_ADDR:	equ	5h
y3_MASK:	equ	8h
; y4 address and mask equates
y4_Bypass_ADDR:	equ	6h
y4_Data_ADDR:	equ	4h
y4_DriveMode_0_ADDR:	equ	104h
y4_DriveMode_1_ADDR:	equ	105h
y4_IntCtrl_0_ADDR:	equ	106h
y4_IntCtrl_1_ADDR:	equ	107h
y4_IntEn_ADDR:	equ	5h
y4_MASK:	equ	10h
; y5 address and mask equates
y5_Bypass_ADDR:	equ	6h
y5_Data_ADDR:	equ	4h
y5_DriveMode_0_ADDR:	equ	104h
y5_DriveMode_1_ADDR:	equ	105h
y5_IntCtrl_0_ADDR:	equ	106h
y5_IntCtrl_1_ADDR:	equ	107h
y5_IntEn_ADDR:	equ	5h
y5_MASK:	equ	20h
; y6 address and mask equates
y6_Bypass_ADDR:	equ	6h
y6_Data_ADDR:	equ	4h
y6_DriveMode_0_ADDR:	equ	104h
y6_DriveMode_1_ADDR:	equ	105h
y6_IntCtrl_0_ADDR:	equ	106h
y6_IntCtrl_1_ADDR:	equ	107h
y6_IntEn_ADDR:	equ	5h
y6_MASK:	equ	40h
; y7 address and mask equates
y7_Bypass_ADDR:	equ	6h
y7_Data_ADDR:	equ	4h
y7_DriveMode_0_ADDR:	equ	104h
y7_DriveMode_1_ADDR:	equ	105h
y7_IntCtrl_0_ADDR:	equ	106h
y7_IntCtrl_1_ADDR:	equ	107h
y7_IntEn_ADDR:	equ	5h
y7_MASK:	equ	80h
; z0 address and mask equates
z0_Bypass_ADDR:	equ	ah
z0_Data_ADDR:	equ	8h
z0_DriveMode_0_ADDR:	equ	108h
z0_DriveMode_1_ADDR:	equ	109h
z0_IntCtrl_0_ADDR:	equ	10ah
z0_IntCtrl_1_ADDR:	equ	10bh
z0_IntEn_ADDR:	equ	9h
z0_MASK:	equ	1h
; Vload1 address and mask equates
Vload1_Bypass_ADDR:	equ	ah
Vload1_Data_ADDR:	equ	8h
Vload1_DriveMode_0_ADDR:	equ	108h
Vload1_DriveMode_1_ADDR:	equ	109h
Vload1_IntCtrl_0_ADDR:	equ	10ah
Vload1_IntCtrl_1_ADDR:	equ	10bh
Vload1_IntEn_ADDR:	equ	9h
Vload1_MASK:	equ	2h
; z2 address and mask equates
z2_Bypass_ADDR:	equ	ah
z2_Data_ADDR:	equ	8h
z2_DriveMode_0_ADDR:	equ	108h
z2_DriveMode_1_ADDR:	equ	109h
z2_IntCtrl_0_ADDR:	equ	10ah
z2_IntCtrl_1_ADDR:	equ	10bh
z2_IntEn_ADDR:	equ	9h
z2_MASK:	equ	4h
; z3 address and mask equates
z3_Bypass_ADDR:	equ	ah
z3_Data_ADDR:	equ	8h
z3_DriveMode_0_ADDR:	equ	108h
z3_DriveMode_1_ADDR:	equ	109h
z3_IntCtrl_0_ADDR:	equ	10ah
z3_IntCtrl_1_ADDR:	equ	10bh
z3_IntEn_ADDR:	equ	9h
z3_MASK:	equ	8h
; z4 address and mask equates
z4_Bypass_ADDR:	equ	ah
z4_Data_ADDR:	equ	8h
z4_DriveMode_0_ADDR:	equ	108h
z4_DriveMode_1_ADDR:	equ	109h
z4_IntCtrl_0_ADDR:	equ	10ah
z4_IntCtrl_1_ADDR:	equ	10bh
z4_IntEn_ADDR:	equ	9h
z4_MASK:	equ	10h
; z5 address and mask equates
z5_Bypass_ADDR:	equ	ah
z5_Data_ADDR:	equ	8h
z5_DriveMode_0_ADDR:	equ	108h
z5_DriveMode_1_ADDR:	equ	109h
z5_IntCtrl_0_ADDR:	equ	10ah
z5_IntCtrl_1_ADDR:	equ	10bh
z5_IntEn_ADDR:	equ	9h
z5_MASK:	equ	20h
; z6 address and mask equates
z6_Bypass_ADDR:	equ	ah
z6_Data_ADDR:	equ	8h
z6_DriveMode_0_ADDR:	equ	108h
z6_DriveMode_1_ADDR:	equ	109h
z6_IntCtrl_0_ADDR:	equ	10ah
z6_IntCtrl_1_ADDR:	equ	10bh
z6_IntEn_ADDR:	equ	9h
z6_MASK:	equ	40h
; z7 address and mask equates
z7_Bypass_ADDR:	equ	ah
z7_Data_ADDR:	equ	8h
z7_DriveMode_0_ADDR:	equ	108h
z7_DriveMode_1_ADDR:	equ	109h
z7_IntCtrl_0_ADDR:	equ	10ah
z7_IntCtrl_1_ADDR:	equ	10bh
z7_IntEn_ADDR:	equ	9h
z7_MASK:	equ	80h