📄 dac6_2.lis
字号:
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
001F cOFFSET: equ 31 ; Conversion term for offset binary to 2's C
0003 bPWRMASK: equ 03h ; Power bitfield in Switched Cap CR3 reg
0030 bCR3: equ 30h ; Except for power bits, CR3 ALWAYS looks
0000 ; like this regardless of SC block type
0000 ; or where the DAC gets mapped.
0000
area text (ROM, REL)
;;---------------------------------------------------------------------------
;; Start / SetPower - Applies power setting to the module's SoCblocs
;;
;; INPUTS: A contains the power setting 0=Off, 1=Low, 2=Med, 3=High
;; OUTUTS: None
;;---------------------------------------------------------------------------
0000 DAC6_2_Start:
0000 _DAC6_2_Start:
0000 DAC6_2_SetPower:
0000 _DAC6_2_SetPower:
0000 2103 and A, bPWRMASK
0002 2930 or A, bCR3 ; Set all other bits in addition to power
0004 609B mov reg[DAC6_2_CR3], A
0006 7F ret
0007
0007 ;;---------------------------------------------------------------------------
0007 ;; WriteBlind
0007 ;; ----------
0007 ;;
0007 ;; Modify the DAC's update value without worrying about the clocks
0007 ;; Lowest overhead, but output may not settle to correct value until the
0007 ;; phi2 of next full cycle following the write.
0007 ;;
0007 ;; INPUTS: The accumulator, A, contains the input in the appropriate format.
0007 ;; The data format is determined by the setting of the DataFormat parameter
0007 ;; in the Device Editor.
0007 ;;
0007 ;; OUTPUTS: Analog output voltage reflects new value
0007 ;;---------------------------------------------------------------------------
0007 DAC6_2_WriteBlind:
0007 _DAC6_2_WriteBlind:
0007
IF DAC6_2_OFFSETBINARY
;; Data is an unsigned byte value in [0..62] (i.e., 63 unique values).
;; Following converts it to 2's complement:
sub A, cOFFSET ; Apply the offset
ENDIF
IF DAC6_2_OFFSETBINARY | DAC6_2_TWOSCOMPLEMENT
;; Data is a byte in standard 2's complement form with value in [-31..+31]
;; Following converts it to Sign & Magnitude form "00smmmmm"
;; where sign, "s", is 1 for negative numbers; 0 for positive
;; and "m" is the magnitude.
0007 64 asl A ; Multiply by 2 and put sign in Carry flag
0008 D007 jnc BlindPositive
000A ;; Neg to pos by "Invert & Add 1" procedure, but data is shifted!
000A 73 cpl A ; bit 0 is a "1" so, following 1 byte "inc" works
000B 74 inc A ; (otherwise, we'd have to "add A, 2")
000C 2940 or A, 40h ; Make it negative by forcing sign bit
000E 8006 jmp BlindMagSet
0010 BlindPositive:
0010 40 nop
0011 40 nop
0012 40 nop
0013 8001 jmp BlindMagSet
0015 BlindMagSet:
0015 67 asr A ; Divide by two to finish up
ENDIF
;; Data is in Sign & Magnitude form.
;; Set FCap and ClockPhase bits
0016 2980 or A, DAC6_2_CR0_HIBITS
0018 6098 mov reg[DAC6_2_CR0], A
001A 7F ret
001B
001B ;;---------------------------------------------------------------------------
001B ;; WriteStall
001B ;; ----------
001B ;;
001B ;; Modify the DAC's update value, stalling the CPU if necessary.
001B ;; This routine should be used with fast analog clocks or when the
001B ;; resulting interrupt latencies, comparable to the update period,
001B ;; can be tolerated comfortably.
001B ;;
001B ;; INPUTS: The accumulator, A, contains the input in the appropriate format.
001B ;; The data format is determined by the setting of the DataFormat parameter
001B ;; in the Device Editor.
001B ;;
001B ;; OUTPUTS: Analog output voltage reflects new value
001B ;;---------------------------------------------------------------------------
001B DAC6_2_WriteStall:
001B _DAC6_2_WriteStall:
001B
IF DAC6_2_OFFSETBINARY
;; Data is an unsigned byte value in [0..62] (i.e., 63 unique values).
;; Following converts it to 2's complement:
sub A, cOFFSET ; Apply the offset
ENDIF
IF DAC6_2_OFFSETBINARY | DAC6_2_TWOSCOMPLEMENT
;; Data is a byte in standard 2's complement form with value in [-31..+31]
;; Following converts it to Sign & Magnitude form "00smmmmm"
;; where sign, "s", is 1 for negative numbers; 0 for positive
;; and "m" is the magnitude.
001B 64 asl A ; Multiply by 2 and put sign in Carry flag
001C D007 jnc StallPositive
001E 73 cpl A ; "Invert" step of complement 2's complement
001F 74 inc A ; "Add 1" step of complement 2's complement
0020 2940 or A, 40h ; Make it negative
0022 8006 jmp StallMagSet
0024 StallPositive:
0024 40 nop
0025 40 nop
0026 40 nop
0027 8001 jmp StallMagSet
0029 StallMagSet:
0029 67 asr A ; Divide by two to finish conversion
ENDIF
;; Data is in Sign & Magnitude form.
;; Set FCap and ClockPhase bits
002A 2980 or A, DAC6_2_CR0_HIBITS
002C 436501 or reg[ASY_CR], ASY_CR_SYNCEN
002F 6098 mov reg[DAC6_2_CR0], A
0031 4165FE and reg[ASY_CR], ~ASY_CR_SYNCEN
0034 7F ret
0035
0035 ;;---------------------------------------------------------------------------
0035 ;; Stop - Cuts power to the user module.
0035 ;;
0035 ;; INPUTS: None
0035 ;; OUTPUTS: None
0035 ;;---------------------------------------------------------------------------
0035 DAC6_2_Stop:
0035 _DAC6_2_Stop:
0035 419BFC and reg[DAC6_2_CR3], ~bPWRMASK
0038 7F ret
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -