📄 dac6_2.lis
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0000 ;;************************************************************************
0000 ;;************************************************************************
0000 ;;
0000 ;; DAC6_2.ASM (from DAC6.asm user module template)
0000 ;; Rev C, 2002 July 25
0000 ;;
0000 ;; Assembler source for 6-bit Switched Capacitor DAC API
0000 ;;
0000 ;; Copyright (c) Cypress MicroSystems 2001-2002. All Rights Reserved.
0000 ;;
0000 ;;************************************************************************
0000 ;;************************************************************************
0000 ;;
0000
export DAC6_2_Start
export _DAC6_2_Start
export DAC6_2_SetPower
export _DAC6_2_SetPower
export DAC6_2_WriteBlind
export _DAC6_2_WriteBlind
export DAC6_2_WriteStall
export _DAC6_2_WriteStall
export DAC6_2_Stop
export _DAC6_2_Stop
;; -----------------------------------------------------------------
;; Register Definitions
;; -----------------------------------------------------------------
;;
;; Uses 1 Switched Cap Block configured as shown. This API depends
;; on knowing the exact personalization of CR0 and CR3 bitfields
;; for time efficiency.
;;
;; * For a Mask/Val pair, this simply indicates that the value is
;; determined by the user either through config-time parameteriza-
;; tion or run-time manipulation.
;;
;; BIT FIELD Mask/Val Function
;; ----------------- ----- --------------------
;; CR0.FCap 80/1 Feedback cap size 32
;; CR0.ClockPhase 40/0 Normal phase
;; CR0.ASign 20/* User parameter
;; CR0.ACap 1F/* User parameter
;;
;; CR1.ACMux E0/2 (SCA) A:VRef High, C:Don't Care
;; CR1.AMux E0/4 (SCB) VRef High
;; CR1.BCap 1F/0 Prune B-input branch
;;
;; CR2.AnalogBus 80/* User Parameter: Output Bus Enable
;; CR2.CmpBus 40/0 Comparator Bus Disable
;; CR2.AutoZero 20/1 Auto-Zero enabled on Phi 1
;; CR2.CCap 1F/0 Prune C-input branch
;;
;; CR3.ARefSelect C0/0 Use AGND (to invert)
;; CR3.FSW1 20/1 Feedback Cap Used
;; CR3.FSW2 10/1 Feedback Cap Grounded for AZ
;; CR3.BMux 0C/0 (SCA) Don't Care - this branch pruned
;; CR3.BSW 08/0 (SCB) Don't Care - this branch pruned
;; CR3.BMux 04/0 (SCB) Don't Care - this branch pruned
;; CR3.PWR 03/* User Parameter: Power, def=OFF
;;
0000 DAC6_2_OFF: equ 00h
0001 DAC6_2_LOWPOWER: equ 01h
0002 DAC6_2_MEDPOWER: equ 02h
0003 DAC6_2_HIGHPOWER: equ 03h
0000
0098 DAC6_2_CR0: equ 98h
0099 DAC6_2_CR1: equ 99h
009A DAC6_2_CR2: equ 9ah
009B DAC6_2_CR3: equ 9bh
0000
0004 DAC6_2_OffsetBinary: equ 04h
0002 DAC6_2_TwosComplement: equ 02h
0001 DAC6_2_SignAndMagnitude: equ 01h
0000 DAC6_2_RawRegister: equ 00h
0000
0003 DAC6_2_DATAFORMAT: equ 3h
0000 DAC6_2_OFFSETBINARY: equ DAC6_2_DATAFORMAT & DAC6_2_OffsetBinary
0002 DAC6_2_TWOSCOMPLEMENT: equ DAC6_2_DATAFORMAT & DAC6_2_TwosComplement
0001 DAC6_2_SIGNANDMAGNITUDE: equ DAC6_2_DATAFORMAT & DAC6_2_SignAndMagnitude
0000
0000 DAC6_2_PHASE_Normal: equ 0
0001 DAC6_2_PHASE_Swapped: equ 1
0000 DAC6_2_PHASE_SWAP: equ DAC6_2_PHASE_Normal
0000
IF DAC6_2_PHASE_SWAP
DAC6_2_CR0_HIBITS: equ C0h
ELSE
0080 DAC6_2_CR0_HIBITS: equ 80h
ENDIF
0010 FlagXIOMask: equ 10h
0008 FlagSuper: equ 08h
0004 FlagCarry: equ 04h
0002 FlagZero: equ 02h
0001 FlagGlobalIE: equ 01h
0000
0000
0000 ;;===================================
0000 ;; Register Space, Bank 0
0000 ;;===================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (WO)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (WO)
0000 ; (Reserved) equ 03h
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (WO)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (WO)
0000 ; (Reserved) equ 07h
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (WO)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (WO)
0000 ; (Reserved) equ 0Bh
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (WO)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (WO)
0000 ; (Reserved) equ 0Fh
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (WO)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (WO)
0000 ; (Reserved) equ 13h
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (WO)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (WO)
0000 ; (Reserved) equ 17h
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 0, Basic Type A
0020 DBA00DR0: equ 20h ; data register 0 (RO)
0021 DBA00DR1: equ 21h ; data register 1 (WO)
0022 DBA00DR2: equ 22h ; data register 2 (RW)
0023 DBA00CR0: equ 23h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 1, Basic Type A
0024 DBA01DR0: equ 24h ; data register 0 (RO)
0025 DBA01DR1: equ 25h ; data register 1 (WO)
0026 DBA01DR2: equ 26h ; data register 2 (RW)
0027 DBA01CR0: equ 27h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 2, Basic Type A
0028 DBA02DR0: equ 28h ; data register 0 (RO)
0029 DBA02DR1: equ 29h ; data register 1 (WO)
002A DBA02DR2: equ 2Ah ; data register 2 (RW)
002B DBA02CR0: equ 2Bh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 3, Basic Type A
002C DBA03DR0: equ 2Ch ; data register 0 (RO)
002D DBA03DR1: equ 2Dh ; data register 1 (WO)
002E DBA03DR2: equ 2Eh ; data register 2 (RW)
002F DBA03CR0: equ 2Fh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 4, Communications Type A
0030 DCA04DR0: equ 30h ; data register 0 (RO)
0031 DCA04DR1: equ 31h ; data register 1 (WO)
0032 DCA04DR2: equ 32h ; data register 2 (RW)
0033 DCA04CR0: equ 33h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 5, Communications Type A
0034 DCA05DR0: equ 34h ; data register 0 (RO)
0035 DCA05DR1: equ 35h ; data register 1 (WO)
0036 DCA05DR2: equ 36h ; data register 2 (RW)
0037 DCA05CR0: equ 37h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 6, Communications Type A
0038 DCA06DR0: equ 38h ; data register 0 (RO)
0039 DCA06DR1: equ 39h ; data register 1 (WO)
003A DCA06DR2: equ 3Ah ; data register 2 (RW)
003B DCA06CR0: equ 3Bh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 7, Communications Type A
003C DCA07DR0: equ 3Ch ; data register 0 (RO)
003D DCA07DR1: equ 3Dh ; data register 1 (WO)
003E DCA07DR2: equ 3Eh ; data register 2 (RW)
003F DCA07CR0: equ 3Fh ; control & status register 0 (RW)
0000
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; analog input multiplexor control (RW)
0000 ; AMX_IN Bit field masks:
00C0 AMX_IN_ACI3: equ C0h ; column 3 input mux
0030 AMX_IN_ACI2: equ 30h ; column 2 input mux
000C AMX_IN_ACI1: equ 0Ch ; column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; column 0 input mux
0000
0000 ; (Reserved) equ 61h ; reserved
0000 ; (Reserved) equ 62h ; reserved
0000
0063 ARF_CR: equ 63h ; analog reference control (RW)
0000 ; ARF_CR Bit field masks:
0080 ARF_CR_BGT: equ 80h ; Bandgap Test
0040 ARF_CR_HBE: equ 40h ; Bias level control
0038 ARF_CR_REF: equ 38h ; Analog array ref control
0004 ARF_CR_APWR: equ 04h ; Analog Power
0003 ARF_CR_SCPWR: equ 03h ; Switched Cap block power
0000
0064 CMP_CR: equ 64h ; comparator control (*)
0000 ; CMP_CR Bit field masks:
0080 CMP_CR_COMP3: equ 80h ; Column 3 comparator state (R)
0040 CMP_CR_COMP2: equ 40h ; Column 2 comparator state (R)
0020 CMP_CR_COMP1: equ 20h ; Column 1 comparator state (R)
0010 CMP_CR_COMP0: equ 10h ; Column 0 comparator state (R)
0008 CMP_CR_AINT3: equ 08h ; Column 3 interrupt source (RW)
0004 CMP_CR_AINT2: equ 04h ; Column 2 interrupt source (RW)
0002 CMP_CR_AINT1: equ 02h ; Column 1 interrupt source (RW)
0001 CMP_CR_AINT0: equ 01h ; Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; analog synchronizaton control (*)
0000 ; ASY_CR Bit field masks:
0007 ASY_CR_SARCOUNT: equ 07h ; SAR support: resolution count (W0)
0008 ASY_CR_SARSIGN: equ 08h ; SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; Stall bit (RW)
0000
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 0
0000 ; (Reserved) equ 70h
0071 ACA00CR0: equ 71h ; Control register 0 (RW)
0072 ACA00CR1: equ 72h ; Control register 1 (RW)
0073 ACA00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 1
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