📄 diffamp2int.lis
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0000 ;;; API for SCBLOCK
0000 ;;; Copyright (c) 2001
0000 ;;; UserModuleID "SCBLOCK"
0000
export DiffAmp2_SCBLK_INT
;; -----------------------------------------------------------------
;; Register Definitions
;; -----------------------------------------------------------------
;; BIT FIELD Mask
;; ----------------- -----
;; CR0.FCap 80
;; CR0.ClockPhase 40
;; CR0.ASign 20
;; CR0.ACap 1F
;;
;; CR1.AMux C0 SCB
;; CR1.ACMux C0 SCA
;; CR1.BCap 1F
;;
;; CR2.AnalogBus 80
;; CR2.CmpBus 40
;; CR2.AutoZero 20
;; CR2.CCap 1F
;;
;; CR3.RefSelect C0
;; CR3.FSW1 20
;; CR3.FSW0 10
;; CR3.BSW 08 SCB
;; CR3.BMux 04 SCB
;; CR3.BMux 0C SCA
;; CR3.Power 03
;;
0088 DiffAmp2_cr0: equ 88h
0089 DiffAmp2_cr1: equ 89h
008A DiffAmp2_cr2: equ 8ah
008B DiffAmp2_cr3: equ 8bh
0064 DiffAmp2_Comp_Ctrl: equ 64h
0000 DiffAmp2_OFF: equ 0
0001 DiffAmp2_LOWPOWER: equ 1
0002 DiffAmp2_MEDPOWER: equ 2
0003 DiffAmp2_HIGHPOWER: equ 3
0000
0000
0000
0000
0000
0000
0010 FlagXIOMask: equ 10h
0008 FlagSuper: equ 08h
0004 FlagCarry: equ 04h
0002 FlagZero: equ 02h
0001 FlagGlobalIE: equ 01h
0000
0000
0000 ;;===================================
0000 ;; Register Space, Bank 0
0000 ;;===================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (WO)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (WO)
0000 ; (Reserved) equ 03h
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (WO)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (WO)
0000 ; (Reserved) equ 07h
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (WO)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (WO)
0000 ; (Reserved) equ 0Bh
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (WO)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (WO)
0000 ; (Reserved) equ 0Fh
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (WO)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (WO)
0000 ; (Reserved) equ 13h
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (WO)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (WO)
0000 ; (Reserved) equ 17h
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 0, Basic Type A
0020 DBA00DR0: equ 20h ; data register 0 (RO)
0021 DBA00DR1: equ 21h ; data register 1 (WO)
0022 DBA00DR2: equ 22h ; data register 2 (RW)
0023 DBA00CR0: equ 23h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 1, Basic Type A
0024 DBA01DR0: equ 24h ; data register 0 (RO)
0025 DBA01DR1: equ 25h ; data register 1 (WO)
0026 DBA01DR2: equ 26h ; data register 2 (RW)
0027 DBA01CR0: equ 27h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 2, Basic Type A
0028 DBA02DR0: equ 28h ; data register 0 (RO)
0029 DBA02DR1: equ 29h ; data register 1 (WO)
002A DBA02DR2: equ 2Ah ; data register 2 (RW)
002B DBA02CR0: equ 2Bh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 3, Basic Type A
002C DBA03DR0: equ 2Ch ; data register 0 (RO)
002D DBA03DR1: equ 2Dh ; data register 1 (WO)
002E DBA03DR2: equ 2Eh ; data register 2 (RW)
002F DBA03CR0: equ 2Fh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 4, Communications Type A
0030 DCA04DR0: equ 30h ; data register 0 (RO)
0031 DCA04DR1: equ 31h ; data register 1 (WO)
0032 DCA04DR2: equ 32h ; data register 2 (RW)
0033 DCA04CR0: equ 33h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 5, Communications Type A
0034 DCA05DR0: equ 34h ; data register 0 (RO)
0035 DCA05DR1: equ 35h ; data register 1 (WO)
0036 DCA05DR2: equ 36h ; data register 2 (RW)
0037 DCA05CR0: equ 37h ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 6, Communications Type A
0038 DCA06DR0: equ 38h ; data register 0 (RO)
0039 DCA06DR1: equ 39h ; data register 1 (WO)
003A DCA06DR2: equ 3Ah ; data register 2 (RW)
003B DCA06CR0: equ 3Bh ; control & status register 0 (RW)
0000
0000 ; Digital PSoC block 7, Communications Type A
003C DCA07DR0: equ 3Ch ; data register 0 (RO)
003D DCA07DR1: equ 3Dh ; data register 1 (WO)
003E DCA07DR2: equ 3Eh ; data register 2 (RW)
003F DCA07CR0: equ 3Fh ; control & status register 0 (RW)
0000
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; analog input multiplexor control (RW)
0000 ; AMX_IN Bit field masks:
00C0 AMX_IN_ACI3: equ C0h ; column 3 input mux
0030 AMX_IN_ACI2: equ 30h ; column 2 input mux
000C AMX_IN_ACI1: equ 0Ch ; column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; column 0 input mux
0000
0000 ; (Reserved) equ 61h ; reserved
0000 ; (Reserved) equ 62h ; reserved
0000
0063 ARF_CR: equ 63h ; analog reference control (RW)
0000 ; ARF_CR Bit field masks:
0080 ARF_CR_BGT: equ 80h ; Bandgap Test
0040 ARF_CR_HBE: equ 40h ; Bias level control
0038 ARF_CR_REF: equ 38h ; Analog array ref control
0004 ARF_CR_APWR: equ 04h ; Analog Power
0003 ARF_CR_SCPWR: equ 03h ; Switched Cap block power
0000
0064 CMP_CR: equ 64h ; comparator control (*)
0000 ; CMP_CR Bit field masks:
0080 CMP_CR_COMP3: equ 80h ; Column 3 comparator state (R)
0040 CMP_CR_COMP2: equ 40h ; Column 2 comparator state (R)
0020 CMP_CR_COMP1: equ 20h ; Column 1 comparator state (R)
0010 CMP_CR_COMP0: equ 10h ; Column 0 comparator state (R)
0008 CMP_CR_AINT3: equ 08h ; Column 3 interrupt source (RW)
0004 CMP_CR_AINT2: equ 04h ; Column 2 interrupt source (RW)
0002 CMP_CR_AINT1: equ 02h ; Column 1 interrupt source (RW)
0001 CMP_CR_AINT0: equ 01h ; Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; analog synchronizaton control (*)
0000 ; ASY_CR Bit field masks:
0007 ASY_CR_SARCOUNT: equ 07h ; SAR support: resolution count (W0)
0008 ASY_CR_SARSIGN: equ 08h ; SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; Stall bit (RW)
0000
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
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