📄 psocconfig.lis
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000C AMD_CR_AMOD2: equ 0Ch ; MASK: Modulation source for analog column 2
0003 AMD_CR_AMOD0: equ 03h ; MASK: Modulation source for analog column 1
0000
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
export LoadConfigInit
export _LoadConfigInit
export LoadConfig_currentsource
export _LoadConfig_currentsource
export NO_SHADOW
export _NO_SHADOW
0010 FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
00FF END_CONFIG_TABLE: equ ffh ;end of config table indicator
0000
AREA psoc_config(rom, rel)
0000 _LoadConfigInit:
0000 LoadConfigInit:
0000
0000 9001 call LoadConfig_currentsource
0002
0002 7F ret
0003
0003 ;
0003 ; Load Configuration currentsource
0003 ;
0003 _LoadConfig_currentsource:
0003 LoadConfig_currentsource:
0003 08 push a
0004 10 push x
0005 7110 or F, FlagXIOMask
0007 5000 mov A, >LoadConfigTBL_currentsource_Bank1 ;load bank 1 table
0009 5700 mov X, <LoadConfigTBL_currentsource_Bank1
000B 900B call LoadConfig ;load the bank 1 values
000D 70EF and F, ~FlagXIOMask
000F 5000 mov A, >LoadConfigTBL_currentsource_Bank0 ;load bank 0 table
0011 5700 mov X, <LoadConfigTBL_currentsource_Bank0
0013 9003 call LoadConfig ;load the bank 0 values
0015 20 pop x
0016 18 pop a
0017 7F ret
0018
0018
0018 ;
0018 ; LoadConfig
0018 ;
0018 ; This function is not exported. It assumes that the address of the table
0018 ; to be loaded is contained in the X and A registers as if a romx instruction
0018 ; is the next instruction to be executed, i.e. lower address in X and uppper
0018 ; address in A. There is no return value.
0018 ;
0018 LoadConfig:
0018 3801 add SP, 1
001A LoadConfigLp:
001A 62E300 mov reg[RES_WDT], 00h
001D 10 push X ;save config table address on stack
001E 08 push A
001F 28 romx ;load config address
0020 39FF cmp A, END_CONFIG_TABLE ;check for end of table
0022 A01A jz EndLoadConfig ;if so, end of load
0024 4F mov X, SP ;save the address away
0025 54FD mov [X-3], A
0027 18 pop A ;retrieve the table address
0028 20 pop X
0029 75 inc X ;advance to the data byte
002A D002 jnc NoOverFlow1 ;check for overflow
002C 74 inc A ;if so, increment MSB
002D NoOverFlow1:
002D 10 push X ;save the config table address again
002E 08 push A
002F 28 romx ;load the config data
0030 4F mov X, SP ;retrieve the config address
0031 59FD mov X, [X-3]
0033 6100 mov reg[X], A ;write the config data
0035 18 pop A ;retrieve the table address
0036 20 pop X
0037 75 inc X ;advance to the next address
0038 D002 jnc NoOverFlow2 ;check for overflow
003A 74 inc A ;if so, increment MSB
003B NoOverFlow2:
003B 8FDE jmp LoadConfigLp ;loop back
003D EndLoadConfig:
003D 18 pop A ;clean up the stack
003E 20 pop X
003F 38FF add SP, -1
0041 7F ret
0042
0042 NO_SHADOW:
0042 _NO_SHADOW:
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