📄 buffer.lis
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0001 CMP_CR_AINT0: equ 01h ; Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; analog synchronizaton control (*)
0000 ; ASY_CR Bit field masks:
0007 ASY_CR_SARCOUNT: equ 07h ; SAR support: resolution count (W0)
0008 ASY_CR_SARSIGN: equ 08h ; SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; Stall bit (RW)
0000
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 0
0000 ; (Reserved) equ 70h
0071 ACA00CR0: equ 71h ; Control register 0 (RW)
0072 ACA00CR1: equ 72h ; Control register 1 (RW)
0073 ACA00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 1
0000 ; (Reserved) equ 74h
0075 ACA01CR0: equ 75h ; Control register 0 (RW)
0076 ACA01CR1: equ 76h ; Control register 1 (RW)
0077 ACA01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 2
0000 ; (Reserved) equ 78h
0079 ACA02CR0: equ 79h ; Control register 0 (RW)
007A ACA02CR1: equ 7Ah ; Control register 1 (RW)
007B ACA02CR2: equ 7Bh ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type A Row 0 Col 3
0000 ; (Reserved) equ 7Ch
007D ACA03CR0: equ 7Dh ; Control register 0 (RW)
007E ACA03CR1: equ 7Eh ; Control register 1 (RW)
007F ACA03CR2: equ 7Fh ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType A Row 1 Col 0
0080 ASA10CR0: equ 80h ; Control register 0 (RW)
0081 ASA10CR1: equ 81h ; Control register 1 (RW)
0082 ASA10CR2: equ 82h ; Control register 2 (RW)
0083 ASA10CR3: equ 83h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType B Row 1 Col 1
0084 ASB11CR0: equ 84h ; Control register 0 (RW)
0085 ASB11CR1: equ 85h ; Control register 1 (RW)
0086 ASB11CR2: equ 86h ; Control register 2 (RW)
0087 ASB11CR3: equ 87h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType A Row 1 Col 2
0088 ASA12CR0: equ 88h ; Control register 0 (RW)
0089 ASA12CR1: equ 89h ; Control register 1 (RW)
008A ASA12CR2: equ 8Ah ; Control register 2 (RW)
008B ASA12CR3: equ 8Bh ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType B Row 1 Col 3
008C ASB13CR0: equ 8Ch ; Control register 0 (RW)
008D ASB13CR1: equ 8Dh ; Control register 1 (RW)
008E ASB13CR2: equ 8Eh ; Control register 2 (RW)
008F ASB13CR3: equ 8Fh ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType B Row 2 Col 0
0090 ASB20CR0: equ 90h ; Control register 0 (RW)
0091 ASB20CR1: equ 91h ; Control register 1 (RW)
0092 ASB20CR2: equ 92h ; Control register 2 (RW)
0093 ASB20CR3: equ 93h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType A Row 2 Col 1
0094 ASA21CR0: equ 94h ; Control register 0 (RW)
0095 ASA21CR1: equ 95h ; Control register 1 (RW)
0096 ASA21CR2: equ 96h ; Control register 2 (RW)
0097 ASA21CR3: equ 97h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType B Row 2 Col 2
0098 ASB22CR0: equ 98h ; Control register 0 (RW)
0099 ASB22CR1: equ 99h ; Control register 1 (RW)
009A ASB22CR2: equ 9Ah ; Control register 2 (RW)
009B ASB22CR3: equ 9Bh ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType A Row 2 Col 3
009C ASA23CR0: equ 9Ch ; Control register 0 (RW)
009D ASA23CR1: equ 9Dh ; Control register 1 (RW)
009E ASA23CR2: equ 9Eh ; Control register 2 (RW)
009F ASA23CR3: equ 9Fh ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
00E0 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
0040 INT_MSK0_Sleep: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0010 INT_MSK0_AColumn3: equ 10h ; MASK: enable/disable Analog col 3 interrupt
0008 INT_MSK0_AColumn2: equ 08h ; MASK: enable/disable Analog col 2 interrupt
0004 INT_MSK0_AColumn1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_AColumn0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VoltageMonitor: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
00E2 INT_VC: equ E2h ; Interrupt vector register (RW)
00E3 RES_WDT: equ E3h ; Watch Dog Timer (RW)
0000
0000 ; DECIMATOR Registers
00E4 DEC_DH: equ E4h ; Data Register (high byte) (RW)
00E5 DEC_DL: equ E5h ; Data Register ( low byte) (RO)
00E6 DEC_CR: equ E6h ; Data Control Register (RW)
0000
0000 ; Multiplier and MAC (Multiply/Accumulate) Unit
00E8 MUL_X: equ E8h ; Multiplier X Register (write) (WO)
00E9 MUL_Y: equ E9h ; Multiplier Y Register (write) (WO)
00EA MUL_DH: equ EAh ; Multiplier Result Data (high byte read) (RO)
00EB MUL_DL: equ EBh ; Multiplier Result Data ( low byte read) (RO)
00EC MAC_X: equ ECh ; MAC X register (write) [also see ACC_DR1](WO)
00ED MAC_Y: equ EDh ; MAC Y register (write) [also see ACC_DR0](WO)
00EE MAC_CL0: equ EEh ; MAC Clear Accum (write)[also see ACC_DR3](WO)
00EF MAC_CL1: equ EFh ; MAC Clear Accum (write)[also see ACC_DR2](WO)
00EC ACC_DR1: equ ECh ; MAC Accumulator (Read, byte 0) (RO)
00ED ACC_DR0: equ EDh ; MAC Accumulator (Read, byte 0) (RO)
00EE ACC_DR3: equ EEh ; MAC Accumulator (Read, byte 0) (RO)
00EF ACC_DR2: equ EFh ; MAC Accumulator (Read, byte 0) (RO)
0000
0000 ; Test Mode mapping of the CPU Flag (F) Register
00F7 CPU_FLAG: equ F7h ; NOTE: Only mapped when in Test Mode !!!
0000
0000
0000 ;------------------------------------------------
0000 ; System Status and Control Register
0000 ;
0000 ; Note: the following register is mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
00FF CPU_SCR: equ FFh ; (*)
0080 CPUSCR_GIEMask: equ 80h ; MASK: flag reg Global Int Enable shadow
0020 CPUSCR_WDRSMask: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPUSCR_PORSMask: equ 10h ; MASK: power-on reset bit PORS
0008 CPUSCR_SleepMask: equ 08h ; MASK: Enable Sleep
0001 CPUSCR_StopMask: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;===================================
0000 ;; Register Space, Bank 1
0000 ;;===================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (WO)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (WO)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (WO)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (WO)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (WO)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (WO)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (WO)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (WO)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (WO)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (WO)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (WO)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (WO)
0000
0000 ; Port 3
000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (WO)
000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (WO)
000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (WO)
000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (WO)
0000
0000 ; Port 4
0010 PRT4DM0: equ 10h ; Port 4 Drive Mode 0 (WO)
0011 PRT4DM1: equ 11h ; Port 4 Drive Mode 1 (WO)
0012 PRT4IC0: equ 12h ; Port 4 Interrupt Control 0 (WO)
0013 PRT4IC1: equ 13h ; Port 4 Interrupt Control 1 (WO)
0000
0000 ; Port 5
0014 PRT5DM0: equ 14h ; Port 5 Drive Mode 0 (WO)
0015 PRT5DM1: equ 15h ; Port 5 Drive Mode 1 (WO)
0016 PRT5IC0: equ 16h ; Port 5 Interrupt Control 0 (WO)
0017 PRT5IC1: equ 17h ; Port 5 Interrupt Control 1 (WO)
0000
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 0, Basic Type A
0020 DBA00FN: equ 20h ; Function Register (RW)
0021 DBA00IN: equ 21h ; Input Register (RW)
0022 DBA00OU: equ 22h ; Output Register (RW)
0000 ; (Reserved) equ 23h
0000
0000 ; Digital PSoC block 1, Basic Type A
0024 DBA01FN: equ 24h ; Function Register (RW)
0025 DBA01IN: equ 25h ; Input Register (RW)
0026 DBA01OU: equ 26h ; Output Register (RW)
0000 ; (Reserved) equ 27h
0000
0000 ; Digital PSoC block 2, Basic Type A
0028 DBA02FN: equ 28h ; Function Register (RW)
0029 DBA02IN: equ 29h ; Input Register (RW)
002A DBA02OU: equ 2Ah ; Output Register (RW)
0000 ; (Reserved) equ 2Bh
0000
0000 ; Digital PSoC block 3, Basic Type A
002C DBA03FN: equ 2Ch ; Function Register (RW)
002D DBA03IN: equ 2Dh ; Input Register (RW)
002E DBA03OU: equ 2Eh ; Output Register (RW)
0000 ; (Reserved) equ 2Fh
0000
0000 ; Digital PSoC block 4, Communications Type A
0030 DCA04FN: equ 30h ; Function Register (RW)
0031 DCA04IN: equ 31h ; Input Register (RW)
0032 DCA04OU: equ 32h ; Output Register (RW)
0000 ; (Reserved) equ 33h
0000
0000 ; Digital PSoC block 5, Communications Type A
0034 DCA05FN: equ 34h ; Function Register (RW)
0035 DCA05IN: equ 35h ; Input Register (RW)
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