buffer.inc

Application Note Abstract The unique configuration of the PSoC&reg switched capacitor blocks allows

;;***********************************************************************
;;***********************************************************************
;;
;; PGA_A.inc
;;
;; Assembler declarations for the PGA_A user module interface
;;
;; Rev B, 2002 Mar 30
;; 
;; Copyright: Cypress MicroSystems 2001-2002. All rights reserved
;;
;;***********************************************************************
;;***********************************************************************


Buffer_OFF:         equ 0
Buffer_LOWPOWER:    equ 1
Buffer_MEDPOWER:    equ 2
Buffer_HIGHPOWER:   equ 3

Buffer_G16_0:       equ 08h
Buffer_G8_00:       equ 18h
Buffer_G5_33:       equ 28h
Buffer_G4_00:       equ 38h
Buffer_G3_20:       equ 48h
Buffer_G2_67:       equ 58h
Buffer_G2_27:       equ 68h
Buffer_G2_00:       equ 78h
Buffer_G1_78:       equ 88h
Buffer_G1_60:       equ 98h
Buffer_G1_46:       equ A8h
Buffer_G1_33:       equ B8h
Buffer_G1_23:       equ C8h
Buffer_G1_14:       equ D8h
Buffer_G1_06:       equ E8h
Buffer_G1_00:       equ F8h
Buffer_G0_93:       equ E0h
Buffer_G0_87:       equ D0h
Buffer_G0_81:       equ C0h
Buffer_G0_75:       equ B0h
Buffer_G0_68:       equ A0h
Buffer_G0_62:       equ 90h
Buffer_G0_56:       equ 80h
Buffer_G0_50:       equ 70h
Buffer_G0_43:       equ 60h
Buffer_G0_37:       equ 50h
Buffer_G0_31:       equ 40h
Buffer_G0_25:       equ 30h
Buffer_G0_18:       equ 20h
Buffer_G0_12:       equ 10h
Buffer_G0_06:       equ 00h

Buffer_GAIN_CR0:    equ 79h
Buffer_GAIN_CR1:    equ 7ah
Buffer_GAIN_CR2:    equ 7bh