📄 calllogger.lst
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(0285) ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0286) ;-------------------------------------------------------------------------
(0287) ; 24 MHz operation is requested. Requires 5V operation.
(0288) ; Only 07h setting is valid (04h | 03h)
(0289) ;-------------------------------------------------------------------------
(0290)
(0291) IF (SUPPLY_VOLTAGE)
(0292) ;-------------------------------------------------------------------------
(0293) ; 4.19 thru 5.0 V is selected
(0294) ;-------------------------------------------------------------------------
(0295)
(0296) IF (TRIP_VOLTAGE ^ 07h)
(0297) ERROR_PSoC TRIP_VOLTAGE must be 4.64V(5.00V) for 24 MHz operation
(0298)
(0299) ENDIF ;(TRIP_VOLTAGE ^ 07h)
(0300)
(0301) ELSE ;!(SUPPLY_VOLTAGE)
(0302) ERROR_PSoC Only valid SMP setting is 5.0 V
(0303)
(0304) ENDIF ;(SUPPLY_VOLTAGE)
(0305) ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0306)
(0307) ;-------------------------------------------------------------------------
(0308) ; But must wait for the SMP to slew from 3.1 to 5 Volts, if SMP selected.
(0309) ;-------------------------------------------------------------------------
(0310) M8C_EnableIntMask INT_MSK0, INT_MSK0_Sleep
(0311)
(0312) IF (SUPPLY_VOLTAGE)
(0313) M8C_SetBank1
(0314) mov reg[OSC_CR0], OSC_CR0_Sleep_512Hz
(0315) M8C_SetBank0
(0316)
(0317) M8C_ClearWDTAndSleep ; Reset the sleep timer
(0318)
(0319) mov reg[INT_VC],0 ; Clear all pending interrupts
(0320) .WaitFor2ms:
(0321) mov A, reg[INT_VC] ; read Interrupt Vector
(0322) jz .WaitFor2ms ; TimeOut occurs on Sleep Timer 2ms
(0323) ENDIF ;(SUPPLY_VOLTAGE)
(0324)
(0325) ;-------------------------------------------------------------------------
(0326) ; Vcc is Stable and Correct, at 5V range. Setup LVD for Brownout
(0327) ;-------------------------------------------------------------------------
(0328)
(0329) M8C_EnableIntMask INT_MSK0, INT_MSK0_VoltageMonitor ; LVD only
(0330)
(0331) ELSE ;!(SWITCH_MODE_PUMP ^ 1) ; SMP is disabled
(0332) ;-------------------------------------------------------------------------
(0333) ; Normal operation with no pump.
(0334) ;-------------------------------------------------------------------------
(0335)
(0336) M8C_EnableIntMask INT_MSK0, INT_MSK0_VoltageMonitor ; LVD only
0076: 43 E0 01 OR REG[224],1
(0337)
(0338) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0339) ;-------------------------------------------------------------------------
(0340) ; < 24 MHz operation is requested. Any reasonable Vcc is OK.
(0341) ;-------------------------------------------------------------------------
(0342)
(0343) ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0344) ;-------------------------------------------------------------------------
(0345) ; 24 MHz operation is requested. Requires 5V operation.
(0346) ;-------------------------------------------------------------------------
(0347)
(0348) IF (SUPPLY_VOLTAGE)
(0349) ; Set the CPU speed to 93.75kHz in order to slow down INT_VC read
(0350) M8C_SetBank1
0079: 71 10 OR F,16
(0351) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_93d7kHz)
007B: 62 E0 07 MOV REG[224],7
(0352) .LVDLoop:
(0353) M8C_SetBank1
007E: 71 10 OR F,16
(0354) mov reg[VLT_CR], 00h ; LVD at 2.95 V (Power Good if >2.95V)
0080: 62 E3 00 MOV REG[227],0
(0355) M8C_SetBank0
0083: 70 EF AND F,239
(0356) mov reg[INT_VC],0 ; Clear LVD interrupt
0085: 62 E2 00 MOV REG[226],0
(0357) M8C_SetBank1
0088: 71 10 OR F,16
(0358) mov reg[VLT_CR], 07h ; Force LVD at 4.64 V (Power Not good if <4.64V)
008A: 62 E3 07 MOV REG[227],7
(0359) M8C_SetBank0 ; Must wait 10 usec before reading INT_VC
008D: 70 EF AND F,239
(0360) mov A, reg[INT_VC]
008F: 5D E2 MOV A,REG[226]
(0361) jz .GoodVcc
0091: A0 03 JZ 0x0095
(0362) jmp .LVDLoop ; Wait for good Vcc
0093: 8F EA JMP 0x007E
(0363) .GoodVcc:
(0364) ;-------------------------------------------------------------------------
(0365) ; Leave LVD at 4.64 V (Required, no exceptions)
(0366) ;-------------------------------------------------------------------------
(0367)
(0368) ELSE ;!(SUPPLY_VOLTAGE)
(0369)
(0370) ERROR_PSoC 24 MHz at other than 5V is invalid.
(0371)
(0372) ENDIF ;(SUPPLY_VOLTAGE)
(0373) ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0374) ENDIF ;(SWITCH_MODE_PUMP ^ 1)
(0375)
(0376) ;-------------------------------------------------------------------------
(0377) ; Disable the Sleep interrupt that was used for timing above.
(0378) ;-------------------------------------------------------------------------
(0379) M8C_DisableIntMask INT_MSK0, INT_MSK0_Sleep
0095: 5D FF MOV A,REG[255]
0097: 70 FE AND F,254
0099: 41 E0 BF AND REG[224],191
009C: 21 80 AND A,128
009E: A0 03 JZ 0x00A2
00A0: 71 01 OR F,1
(0380)
(0381) ;-------------------------------------------------------------------------
(0382) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0383) ;-------------------------------------------------------------------------
(0384)
(0385) M8C_SetBank1
00A2: 71 10 OR F,16
(0386) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
00A4: 62 E0 03 MOV REG[224],3
(0387) M8C_SetBank0
00A7: 70 EF AND F,239
(0388)
(0389) ;-------------------------------------------------------------------------
(0390) ; Global Interrupt are NOT enabled, this should be done in main().
(0391) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0392) ; Global Interrupts should be as soon as possible in main().
(0393) ;-------------------------------------------------------------------------
(0394)
(0395) lcall _main ; Call main
00A9: 7C 01 F6 LCALL _main
(0396)
(0397) __Exit:
(0398) jmp __Exit ; Wait here till power is turned off
00AC: 8F FF JMP 0x00AC
(0399)
(0400)
(0401)
(0402) ;-----------------------------------------------------------------------------
(0403) ; C Runtime Environment Initialization
(0404) ; The following code is conditionally assembled.
(0405) ;-----------------------------------------------------------------------------
(0406)
(0407) IF (C_LANGUAGE_SUPPORT)
(0408)
(0409) InitCRunTime:
(0410) ;-----------------------------
(0411) ; clear bss segment
(0412) ;-----------------------------
(0413) mov A,0
00AE: 50 00 MOV A,0
(0414) mov [__r0],<__bss_start
00B0: 55 00 01 MOV [__r0],1
(0415) BssLoop:
(0416) cmp [__r0],<__bss_end
00B3: 3C 00 76 CMP [__r0],118
(0417) jz BssDone
00B6: A0 05 JZ 0x00BC
(0418) mvi [__r0],A
00B8: 3F 00 MVI [__r0],A
(0419) jmp BssLoop
00BA: 8F F8 JMP 0x00B3
(0420) BssDone:
(0421) ;----------------------------
(0422) ; copy idata to data segment
(0423) ;----------------------------
(0424) mov A,>__idata_start
00BC: 50 01 MOV A,1
(0425) mov X,<__idata_start
00BE: 57 B4 MOV X,180
(0426) mov [__r0],<__data_start
00C0: 55 00 00 MOV [__r0],0
(0427) IDataLoop:
(0428) cmp [__r0],<__data_end
00C3: 3C 00 00 CMP [__r0],0
(0429) jz IDataDone
00C6: A0 0B JZ 0x00D2
(0430) push A
00C8: 08 PUSH A
(0431) romx
00C9: 28 ROMX
(0432) mvi [__r0],A
00CA: 3F 00 MVI [__r0],A
(0433) pop A
00CC: 18 POP A
(0434) inc X
00CD: 75 INC X
(0435) adc A,0
00CE: 09 00 ADC A,0
(0436) jmp IDataLoop
00D0: 8F F2 JMP 0x00C3
(0437) IDataDone:
(0438) ret
00D2: 7F RET
00D3: 30 HALT
00D4: 30 HALT
00D5: 30 HALT
00D6: 30 HALT
00D7: 30 HALT
00D8: 30 HALT
00D9: 30 HALT
00DA: 30 HALT
00DB: 30 HALT
00DC: 30 HALT
00DD: 30 HALT
00DE: 30 HALT
00DF: 30 HALT
00E0: 30 HALT
00E1: 30 HALT
00E2: 30 HALT
00E3: 30 HALT
00E4: 30 HALT
00E5: 30 HALT
00E6: 30 HALT
00E7: 30 HALT
00E8: 30 HALT
00E9: 30 HALT
00EA: 30 HALT
00EB: 30 HALT
00EC: 30 HALT
00ED: 30 HALT
00EE: 30 HALT
00EF: 30 HALT
00F0: 30 HALT
00F1: 30 HALT
00F2: 30 HALT
00F3: 30 HALT
00F4: 30 HALT
00F5: 30 HALT
00F6: 30 HALT
00F7: 30 HALT
00F8: 30 HALT
00F9: 30 HALT
00FA: 30 HALT
00FB: 30 HALT
00FC: 30 HALT
00FD: 30 HALT
00FE: 30 HALT
00FF: 30 HALT
0100: 30 HALT
0101: 30 HALT
0102: 30 HALT
0103: 30 HALT
0104: 30 HALT
0105: 30 HALT
0106: 61 00 MOV REG[X+0],A
0108: 60 00 MOV REG[0],A
010A: 62 00 63 MOV REG[0],99
010D: 00 SSC
010E: E1 F9 JACC 0x0308
0110: 00 SSC
0111: 90 01 CALL 0x0114
0113: 21 02 AND A,2
0115: 01 03 ADD A,3
0117: 00 SSC
0118: 04 00 ADD [__r0],A
011A: 05 03 ADD [X+3],A
011C: 06 00 07 ADD [__r0],7
011F: 01 08 ADD A,8
0121: 10 PUSH X
0122: 09 EF ADC A,239
0124: 0A 00 ADC A,[__r0]
0126: 0B 00 ADC A,[X+0]
0128: 0C 00 ADC [__r0],A
012A: 0D 00 ADC [X+0],A
012C: 0E 00 0F ADC [__r0],15
012F: 00 SSC
0130: 10 PUSH X
0131: 00 SSC
0132: 11 00 SUB A,0
0134: 12 00 SUB A,[__r0]
0136: 13 00 SUB A,[X+0]
0138: 14 00 SUB [__r0],A
013A: 15 00 SUB [X+0],A
013C: 16 00 17 SUB [__r0],23
013F: 00 SSC
0140: E3 87 JACC 0x04C8
0142: 20 POP X
0143: 01 21 ADD A,33
0145: 16 22 00 SUB [34],0
0148: 24 21 AND [33],A
014A: 25 36 AND [X+54],A
014C: 26 04 28 AND [4],40
014F: 01 29 ADD A,41
0151: 18 POP A
0152: 2A 00 OR A,[__r0]
0154: 2C 21 OR [33],A
0156: 2D 38 OR [X+56],A
0158: 2E 00 30 OR [__r0],48
015B: 21 31 AND A,49
015D: 13 32 SUB A,[X+50]
015F: 04 38 ADD [56],A
0161: 05 39 ADD [X+57],A
0163: D6 3A JNC 0x079E
0165: 00 SSC
0166: 3C 0D 3D CMP [13],61
0169: 06 3E 07 ADD [62],7
016C: FF 60 INDEX 0x00CE
016E: 28 ROMX
016F: 64 ASL A
0170: 00 SSC
0171: 63 05 65 MOV REG[X+5],101
0174: 00 SSC
0175: E6 00 JACC 0x0776
0177: 02 B0 ADD A,[176]
0179: 01 01 ADD A,1
017B: 06 00 05 ADD [__r0],5
017E: 01 0A ADD A,10
0180: 00 SSC
0181: 09 00 ADC A,0
0183: 0E 00 0D ADC [__r0],13
0186: 00 SSC
0187: 12 00 SUB A,[__r0]
0189: 11 00 SUB A,0
018B: 16 00 15 SUB [__r0],21
018E: 00 SSC
018F: 23 00 AND A,[X+0]
0191: 21 F9 AND A,249
0193: 22 7C AND A,[124]
0195: 27 00 25 AND [X+0],37
0198: 00 SSC
0199: 26 00 2B AND [__r0],43
019C: 00 SSC
019D: 29 57 OR A,87
019F: 2A 2C OR A,[44]
01A1: 2F 00 2D OR [X+0],45
01A4: 02 2E ADD A,[46]
01A6: 01 31 ADD A,49
01A8: 3B 32 CMP A,[X+50]
01AA: 1E 39 00 SBB [57],0
01AD: 3A 00 CMP A,[__r0]
01AF: 3D 00 3E CMP [X+0],62
01B2: 00 SSC
01B3: FF 90 INDEX 0x0145
FILE: lib\psocconfig.asm
(0001) ;
(0002) ; PSoCConfig.asm
(0003) ;
(0004) ; Version 0.84
(0005) ; Data: 19 December, 2000
(0006) ; Copyright Cypress MicroSystems 2000
(0007) ;
(0008) ; This file is generated by the Device Editor on Application Generation.
(0009) ; It contains code which loads the configuration data table generated in
(0010) ; the file PSoCConfigTBL.asm
(0011) ;
(0012) ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
(0013) ; Edits to this file will not be preserved.
(0014) ;
(0015) include "m8c.inc"
(0016)
(0017) export LoadConfigInit
(0018) export _LoadConfigInit
(0019) export LoadConfig_calllogger
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