📄 pwm8_1.lis
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0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0010 bPWM8_1_INT_MASK: equ 10h
0000 ;PWM8 interrupt address
00E1 PWM8_1_INT_REG: equ 0e1h
0000
0000
0000 ;---------------------------------
0000 ; Registers used by PWM8
0000 ;---------------------------------
0033 PWM8_1_CONTROL_REG: equ 33h ;Control register
0030 PWM8_1_COUNTER_REG: equ 30h ;Counter register
0031 PWM8_1_PERIOD_REG: equ 31h ;Period value register
0032 PWM8_1_PWIDTH_REG: equ 32h ;PulseWidth register
0030 PWM8_1_FUNC_REG: equ 30h ;Function register
0031 PWM8_1_INPUT_REG: equ 31h ;Input register
0032 PWM8_1_OUTPUT_REG: equ 32h ;Output register
0000
0000 ; end of file
0000
area text (ROM, REL)
;-------------------------------------------------------------------
; Declare the functions global for both assembler and C compiler.
;
; Note that there are two names for each API. First name is
; assembler reference. Name with underscore is name refence for
; C compiler. Calling function in C source code does not require
; the underscore.
;-------------------------------------------------------------------
export PWM8_1_EnableInt
export _PWM8_1_EnableInt
export PWM8_1_DisableInt
export _PWM8_1_DisableInt
export PWM8_1_Start
export _PWM8_1_Start
export PWM8_1_Stop
export _PWM8_1_Stop
export PWM8_1_WritePeriod
export _PWM8_1_WritePeriod
export PWM8_1_WritePulseWidth
export _PWM8_1_WritePulseWidth
export bPWM8_1_ReadPulseWidth
export _bPWM8_1_ReadPulseWidth
export bPWM8_1_ReadCounter
export _bPWM8_1_ReadCounter
;-----------
; EQUATES
;-----------
0001 bfCONTROL_REG_START_BIT: equ 1 ; Control register start bit
000F bfINPUT_REG_CLOCK_MASK: equ 0Fh ; input register clock mask
0000
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: PWM8_1_EnableInt
0000 ;
0000 ; DESCRIPTION:
0000 ; Enables this PWM's interrupt by setting the interrupt enable mask bit
0000 ; associated with this User Module. Remember to call the global interrupt
0000 ; enable function by using the macro: M8C_EnableGInt.
0000 ;
0000 ; ARGUMENTS:
0000 ; none.
0000 ;
0000 ; RETURNS:
0000 ; none.
0000 ;
0000 ; SIDE EFFECTS:
0000 ; none.
0000 ;
0000 ; THEORY of OPERATION:
0000 ; Sets the specific user module interrupt enable mask bit.
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 PWM8_1_EnableInt:
0000 _PWM8_1_EnableInt:
0000 43E110 or reg[PWM8_1_INT_REG], bPWM8_1_INT_MASK
0003 7F ret
0004
0004
0004 ;-----------------------------------------------------------------------------
0004 ; FUNCTION NAME: PWM8_1_DisableInt
0004 ;
0004 ; DESCRIPTION:
0004 ; Disables this PWM's interrupt by clearing the interrupt enable mask bit
0004 ; associated with this User Module.
0004 ;
0004 ; ARGUMENTS:
0004 ; none.
0004 ;
0004 ; RETURNS:
0004 ; none.
0004 ;
0004 ; SIDE EFFECTS:
0004 ; none.
0004 ;
0004 ; THEORY of OPERATION:
0004 ; Clears the specific user module interrupt enable mask bit.
0004 ;
0004 ;-----------------------------------------------------------------------------
0004 PWM8_1_DisableInt:
0004 _PWM8_1_DisableInt:
if DISABLE_INT_FIX
0004 5DFF mov A, reg[CPU_SCR] ; save the current Global interrupt state
0006 70FE and F, ~FlagGlobalIE
endif
0008 41E1EF and reg[PWM8_1_INT_REG], ~bPWM8_1_INT_MASK ; disable specified interrupt enable bit
if DISABLE_INT_FIX
000B 2180 and A, CPUSCR_GIEMask ; determine if global interrupt was set
000D A003 jz . + 4 ; jump if global interrupt disabled
000F 7101 or F, FlagGlobalIE
endif
0011 7F ret
0012
0012
0012 ;-----------------------------------------------------------------------------
0012 ; FUNCTION NAME: PWM8_1_Start
0012 ;
0012 ; DESCRIPTION:
0012 ; Sets the start bit in the Control register of this user module. The
0012 ; PWM will begin counting on the next input clock as soon as the
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