📄 psocgpioint.lis
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00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0010 bPWM8_1_INT_MASK: equ 10h
0000 ;PWM8 interrupt address
00E1 PWM8_1_INT_REG: equ 0e1h
0000
0000
0000 ;---------------------------------
0000 ; Registers used by PWM8
0000 ;---------------------------------
0033 PWM8_1_CONTROL_REG: equ 33h ;Control register
0030 PWM8_1_COUNTER_REG: equ 30h ;Counter register
0031 PWM8_1_PERIOD_REG: equ 31h ;Period value register
0032 PWM8_1_PWIDTH_REG: equ 32h ;PulseWidth register
0030 PWM8_1_FUNC_REG: equ 30h ;Function register
0031 PWM8_1_INPUT_REG: equ 31h ;Input register
0032 PWM8_1_OUTPUT_REG: equ 32h ;Output register
0000
0000 ; end of file
0000 E2_WR_ARG_cTemperature: equ 0 ; chip temperature
0001 E2_WR_ARG_wByteCount: equ 1 ; Byte Count to Write
0003 E2_WR_ARG_pbData: equ 3 ; Data buffer with data to write
0005 E2_WR_ARG_wAddr: equ 5 ; Address offset in E2PROM to write
0007 E2_WR_ARG_STACK_FRAME_SIZE: equ 7 ; SIZE of the argument list in stack frame
0007 E2_CALLER_RETURN_ADDRESS: equ 7 ; callers return address - place holder
0000
0000 ;-------------------------------------
0000 ; Return Values
0000 ;-------------------------------------
0000 NOERROR: equ 0 ; Successfull completion
FFFFFFFF FAILURE: equ -1 ; Error condition
FFFFFFFE STACKOVERFLOW: equ -2 ; Error Stack Overflow
0000
0000
0000
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: E2Read
0000 ;
0000 ; DESCRIPTION:
0000 ; Reads the specified E2PROM data at offset=wAddr for wByteCount bytes and
0000 ; places the data read into the RAM buffer pbDataDest.
0000 ;
0000 ; On entry - NOTE two entry points!!!
0000 ; A must contain the E2PROM device First block Id
0000 ; X must point to calling arguments in the following offset from X:
0000 ; wByteCount 0 2-bytes
0000 ; pbDataDest 2 2-bytes
0000 ; wAddr: 4 2-bytes
0000 ;
0000 ; Prototype in C is:
0000 ;
0000 ; #pragma fastcall E2Read
0000 ; void E2Read( BYTE bFirstBlockId, WORD wAddr, BYTE * pbDataDest, WORD wByteCount );
0000 ;
0000 ; (!!!note that C places arguments Right-to-Left onto the stack!!!)
0000 ;
0000 ; Easiest method to call from assembly is as follows:
0000 ; push X
0000 ; mov X, SP
0000 ; push <wByteCount>
0000 ; push <wByteCount+1>
0000 ; push <0> ; MSB of pbDataDest is always 0
0000 ; push <pbDataDest>
0000 ; push <wAddr>
0000 ; push <wAddr+1>
0000 ; mov A, <FirstBlockId>
0000 ; call E2Read
0000 ; add SP, -E2_RD_ARG_STACK_FRAME_SIZE
0000 ; pop X
0000 ;
0000 ; where <> refers to any addressing mode or number of instructions to
0000 ; place the referenced data on the stack frame.
0000 ;
0000 ; Other method is to create a stack frame using the defined equates and
0000 ; load them into the stack frame using [X+E2_RD_ARG_*] offset addressing mode.
0000 ;
0000 ; ARGUMENTS:
0000 ;
0000 ; bFirstBlockId BYTE - first block ID of E2PROM device
0000 ; wAddr: WORD - relative OFFSET in defined E2PROM to read data
0000 ; pbDataDest: BYTE * - pointer to the RAM buffer to place read data
0000 ; wByteCount: WORD - number of bytes to read from E2PROM
0000 ;
0000 ; RETURNS: NONE.
0000 ;
0000 ; SIDE EFFECTS: NONE.
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 E2_RD_ARG_wByteCount: equ 0 ; Byte Count to Read
0002 E2_RD_ARG_pbDataDest: equ 2 ; Data buffer to store read data
0004 E2_RD_ARG_wAddr: equ 4 ; Address offset in E2PROM to Read
0006 E2_RD_ARG_STACK_FRAME_SIZE: equ 6 ; SIZE of argument list in stack frame
0000
0000 ;--------------------
0000 ; End of File
0000 ;--------------------
0000
0000 ;----------------------------------------
0000 ; E2PROM_1 instance parameters
0000 ;----------------------------------------
0040 E2PROM_1_START_BLOCK: equ 40h ; Absolute address of E2PROM device
1000 E2PROM_1_START_ADDR: equ 40h * 64 ; Size of E2PROM device
0000
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