calllogger_globalparams.inc

Application Note Abstract This Application Note introduces a complete and detailed PSoC&reg project

;
;	This file contains equates to support oscillator register initialization
;

CPU_CLOCK:				equ	0h		;CPU clock value
CPU_CLOCK_MASK:			equ	7h		;CPU clock mask
CPU_CLOCK_JUST:			equ	0h		;CPU clock value justified
SELECT_32K:				equ	0h		;32K select value
SELECT_32K_MASK:		equ	80h		;32K select mask
SELECT_32K_JUST:		equ	0h		;32K select value justified
PLL_MODE:				equ	0h		;PLL mode value
PLL_MODE_MASK:			equ	40h		;PLL mode mask
PLL_MODE_JUST:			equ	0h		;PLL mode value justified
SLEEP_TIMER:			equ	0h		;Sleep Timer value
SLEEP_TIMER_MASK:		equ	18h		;Sleep Timer mask
SLEEP_TIMER_JUST:		equ	0h		;Sleep Timer value justified
SWITCH_MODE_PUMP:		equ	1h		;Switch Mode Pump setting
SWITCH_MODE_PUMP_MASK:	equ	80h		;Switch Mode Pump mask
SWITCH_MODE_PUMP_JUST:	equ	80h	;Switch Mode Pump justified
TRIP_VOLTAGE:			equ	7h	;Trip Voltage
SUPPLY_VOLTAGE:			equ	1h		;Supply Voltage 1 = 5.0V
								;0 = 3.3V
COMM_RX_PRESENT:		equ	1		;1 = TRUE

CLOCK_DIV_24V1:			equ	fh	;24V1 clock divider
CLOCK_DIV_24V1_MASK:	equ	f0h	;24V1 clock divider mask
CLOCK_DIV_24V1_JUST:	equ	f0h	;24V1 clock divider justified
CLOCK_DIV_24V2:			equ	9h	;24V2 clock divider
CLOCK_DIV_24V2_MASK:	equ	fh	;24V2 clock divider mask
CLOCK_DIV_24V2_JUST:	equ	9h	;24V2 clock divider justified
ANALOG_BUFFER_PWR:		equ	0h	;Analog buffer power level
ANALOG_BUFFER_PWR_MASK:	equ	1h	;Analog buffer power level mask
ANALOG_BUFFER_PWR_JUST:	equ	0h	;Analog buffer power level justified
ANALOG_POWER:			equ	5h	;Analog power control
ANALOG_POWER_MASK:		equ	7h	;Analog power control mask
ANALOG_POWER_JUST:		equ	5h	;Analog power control justified
OP_AMP_BIAS:			equ	0h	;Op amp bias level
OP_AMP_BIAS_MASK:		equ	40h	;Op amp bias level mask
OP_AMP_BIAS_JUST:		equ	0h	;Op amp bias level justified
REF_MUX:				equ	0h	;Ref mux setting
REF_MUX_MASK:			equ	38h	;Ref mux setting mask
REF_MUX_JUST:			equ	0h	;Ref mux setting justified
;
; write only registers
;
ANALOG_IO_CONTROL:	equ 0h	;Analog IO Control register (ABF_CR)
PORT_0_BYPASS:		equ b0h	;Port 0 bypass register (PRT0GS)
PORT_0_DRIVE_0:		equ 90h	;Port 0 drive mode 0 register (PRT0DM0)
PORT_0_DRIVE_1:		equ 20h	;Port 0 drive mode 1 register (PRT0DM1)
PORT_0_INTENABLE:	equ 1h	;Port 0 interrupt enable register (PRT0IE)
PORT_0_INTCTRL_0:	equ 1h	;Port 0 interrupt control 0 register (PRT0IC0)
PORT_0_INTCTRL_1:	equ 0h	;Port 0 interrupt control 1 register (PRT0IC1)
PORT_1_BYPASS:		equ 0h	;Port 1 bypass register (PRT1GS)
PORT_1_DRIVE_0:		equ 0h	;Port 1 drive mode 0 register (PRT1DM0)
PORT_1_DRIVE_1:		equ 2h	;Port 1 drive mode 1 register (PRT1DM1)
PORT_1_INTENABLE:	equ 1h	;Port 1 interrupt enable register (PRT1IE)
PORT_1_INTCTRL_0:	equ 0h	;Port 1 interrupt control 0 register (PRT1IC0)
PORT_1_INTCTRL_1:	equ 1h	;Port 1 interrupt control 1 register (PRT1IC1)
PORT_2_BYPASS:		equ 0h	;Port 2 bypass register (PRT2GS)
PORT_2_DRIVE_0:		equ 10h	;Port 2 drive mode 0 register (PRT2DM0)
PORT_2_DRIVE_1:		equ efh	;Port 2 drive mode 1 register (PRT2DM1)
PORT_2_INTENABLE:	equ 0h	;Port 2 interrupt enable register (PRT2IE)
PORT_2_INTCTRL_0:	equ 0h	;Port 2 interrupt control 0 register (PRT2IC0)
PORT_2_INTCTRL_1:	equ 0h	;Port 2 interrupt control 1 register (PRT2IC1)
PORT_3_BYPASS:		equ 0h	;Port 3 bypass register (PRT3GS)
PORT_3_DRIVE_0:		equ 0h	;Port 3 drive mode 0 register (PRT3DM0)
PORT_3_DRIVE_1:		equ 0h	;Port 3 drive mode 1 register (PRT3DM1)
PORT_3_INTENABLE:	equ 0h	;Port 3 interrupt enable register (PRT3IE)
PORT_3_INTCTRL_0:	equ 0h	;Port 3 interrupt control 0 register (PRT3IC0)
PORT_3_INTCTRL_1:	equ 0h	;Port 3 interrupt control 1 register (PRT3IC1)
PORT_4_BYPASS:		equ 0h	;Port 4 bypass register (PRT4GS)
PORT_4_DRIVE_0:		equ 0h	;Port 4 drive mode 0 register (PRT4DM0)
PORT_4_DRIVE_1:		equ 0h	;Port 4 drive mode 1 register (PRT4DM1)
PORT_4_INTENABLE:	equ 0h	;Port 4 interrupt enable register (PRT4IE)
PORT_4_INTCTRL_0:	equ 0h	;Port 4 interrupt control 0 register (PRT4IC0)
PORT_4_INTCTRL_1:	equ 0h	;Port 4 interrupt control 1 register (PRT4IC1)
PORT_5_BYPASS:		equ 0h	;Port 5 bypass register (PRT5GS)
PORT_5_DRIVE_0:		equ 0h	;Port 5 drive mode 0 register (PRT5DM0)
PORT_5_DRIVE_1:		equ 0h	;Port 5 drive mode 1 register (PRT5DM1)
PORT_5_INTENABLE:	equ 0h	;Port 5 interrupt enable register (PRT5IE)
PORT_5_INTCTRL_0:	equ 0h	;Port 5 interrupt control 0 register (PRT5IC0)
PORT_5_INTCTRL_1:	equ 0h	;Port 5 interrupt control 1 register (PRT5IC1)