main.lss

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main.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00001b18  00000000  00000000  00008000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .bss          00000008  40000000  40000000  00009b18  2**1
                  ALLOC
  2 .stack        00001024  40000100  40000100  00009b18  2**0
                  ALLOC
  3 .comment      0000010e  00000000  00000000  00009b18  2**0
                  CONTENTS, READONLY
  4 .debug_aranges 00000140  00000000  00000000  00009c28  2**3
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_pubnames 000002b9  00000000  00000000  00009d68  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_info   000012d7  00000000  00000000  0000a021  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_abbrev 000006bd  00000000  00000000  0000b2f8  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_line   000006b4  00000000  00000000  0000b9b5  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_frame  00000418  00000000  00000000  0000c06c  2**2
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_str    0000058a  00000000  00000000  0000c484  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    000010a2  00000000  00000000  0000ca0e  2**0
                  CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:

00000000 <_boot>:

// Runtime Interrupt Vectors
// -------------------------
Vectors:
        b     _start                    // reset - _start
       0:	ea000015 	b	5c <_mainCRTStartup>
        ldr   pc,_undf                  // undefined - _undf
       4:	e59ff014 	ldr	pc, [pc, #20]	; 20 <_undf>
        ldr   pc,_swi		            // SWI - _swi
       8:	e59ff014 	ldr	pc, [pc, #20]	; 24 <_swi>
        ldr   pc,_pabt                  // program abort - _pabt
       c:	e59ff014 	ldr	pc, [pc, #20]	; 28 <_pabt>
        ldr   pc,_dabt                  // data abort - _dabt
      10:	e59ff014 	ldr	pc, [pc, #20]	; 2c <_dabt>
        nop
      14:	e1a00000 	nop			(mov r0,r0)
        ldr   pc,[pc,#-0xFF0]           // IRQ - read the VIC
      18:	e51ffff0 	ldr	pc, [pc, #-4080]	; fffff030 <_stack+0xbfffdf0c>
        ldr   pc,_fiq                   // FIQ - _fiq
      1c:	e59ff010 	ldr	pc, [pc, #16]	; 34 <_fiq>

00000020 <_undf>:
      20:	81000004 	tsthi	r0, r4

00000024 <_swi>:
      24:	81000008 	tsthi	r0, r8

00000028 <_pabt>:
      28:	8100000c 	tsthi	r0, ip

0000002c <_dabt>:
      2c:	81000010 	tsthi	r0, r0, lsl r0

00000030 <_irq>:
      30:	81000018 	tsthi	r0, r8, lsl r0

00000034 <_fiq>:
      34:	8100001c 	tsthi	r0, ip, lsl r0

00000038 <__undf>:

// Use this group for development
_undf:  .word 0x81000004                    // undefined
_swi:   .word 0x81000008                     // SWI
_pabt:  .word 0x8100000C                    // program abort
_dabt:  .word 0x81000010                    // data abort
_irq:   .word 0x81000018                     // IRQ
_fiq:   .word 0x8100001C                     // FIQ

__undf: b     .				            // undefined
      38:	eafffffe 	b	38 <__undf>

0000003c <__swi>:
__swi:  b     .						    // SWI
      3c:	eafffffe 	b	3c <__swi>

00000040 <__pabt>:
__pabt: b     .            	   		    // program abort
      40:	eafffffe 	b	40 <__pabt>

00000044 <__dabt>:
__dabt: b     .       					// data abort
      44:	eafffffe 	b	44 <__dabt>

00000048 <__irq>:
__irq:  b     .							// IRQ
      48:	eafffffe 	b	48 <__irq>

0000004c <__fiq>:
__fiq:  b     .							// FIQ
      4c:	eafffffe 	b	4c <__fiq>

00000050 <_swiirq>:

        .size _boot, . - _boot
        .endfunc


// Setup the operating mode & stack.
// ---------------------------------
        .global _start, start, _mainCRTStartup
        .func   _start

_swiirq:
swiirq:
        ldr   r10,=swiirqp
      50:	e59fa088 	ldr	sl, [pc, #136]	; e0 <.text+0xe0>
        mov   lr,pc
      54:	e1a0e00f 	mov	lr, pc
        bx    r10                       // enter main()
      58:	e12fff1a 	bx	sl

0000005c <_mainCRTStartup>:

_start:
start:
_mainCRTStartup:

// Initialize Interrupt System
// - Set stack location for each mode
// - Leave in System Mode with Interrupts Disabled
// -----------------------------------------------
        ldr   r0,=_stack
      5c:	e59f0080 	ldr	r0, [pc, #128]	; e4 <.text+0xe4>
        msr   CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode
      60:	e321f0db 	msr	CPSR_c, #219	; 0xdb
        mov   sp,r0
      64:	e1a0d000 	mov	sp, r0
        sub   r0,r0,#UND_STACK_SIZE
      68:	e2400004 	sub	r0, r0, #4	; 0x4
        msr   CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode
      6c:	e321f0d7 	msr	CPSR_c, #215	; 0xd7
        mov   sp,r0
      70:	e1a0d000 	mov	sp, r0
        sub   r0,r0,#ABT_STACK_SIZE
      74:	e2400004 	sub	r0, r0, #4	; 0x4
        msr   CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode
      78:	e321f0d1 	msr	CPSR_c, #209	; 0xd1
        mov   sp,r0
      7c:	e1a0d000 	mov	sp, r0
        sub   r0,r0,#FIQ_STACK_SIZE
      80:	e2400004 	sub	r0, r0, #4	; 0x4
        msr   CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode
      84:	e321f0d2 	msr	CPSR_c, #210	; 0xd2
        mov   sp,r0
      88:	e1a0d000 	mov	sp, r0
        sub   r0,r0,#IRQ_STACK_SIZE
      8c:	e2400080 	sub	r0, r0, #128	; 0x80
        msr   CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode
      90:	e321f0d3 	msr	CPSR_c, #211	; 0xd3
        mov   sp,r0
      94:	e1a0d000 	mov	sp, r0
        sub   r0,r0,#SVC_STACK_SIZE
      98:	e2400004 	sub	r0, r0, #4	; 0x4
        msr   CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode
      9c:	e321f0df 	msr	CPSR_c, #223	; 0xdf
        mov   sp,r0
      a0:	e1a0d000 	mov	sp, r0

// Copy initialized data to its execution address in RAM
// -----------------------------------------------------
#ifdef ROM_RUN
        ldr   r1,=_etext                // -> ROM data start
        ldr   r2,=_data                 // -> data start
        ldr   r3,=_edata                // -> end of data
1:      cmp   r2,r3                     // check if data to move
        ldrlo r0,[r1],#4                // copy it
        strlo r0,[r2],#4
        blo   1b                        // loop until done
#endif
// Clear .bss
// ----------
        mov   r0,#0                     // get a zero
      a4:	e3a00000 	mov	r0, #0	; 0x0
        ldr   r1,=__bss_start           // -> bss start
      a8:	e59f1038 	ldr	r1, [pc, #56]	; e8 <.text+0xe8>
        ldr   r2,=__bss_end__           // -> bss end
      ac:	e59f2038 	ldr	r2, [pc, #56]	; ec <.text+0xec>
2:      cmp   r1,r2                     // check if data to clear
      b0:	e1510002 	cmp	r1, r2
        strlo r0,[r1],#4                // clear 4 bytes
      b4:	34810004 	strcc	r0, [r1], #4
        blo   2b                        // loop until done
      b8:	3afffffc 	bcc	b0 <IRQ_STACK_SIZE+0x30>

// Call main program: main(0)
// --------------------------
        mov   r0,#0                     // no arguments (argc = 0)
      bc:	e3a00000 	mov	r0, #0	; 0x0
        mov   r1,r0
      c0:	e1a01000 	mov	r1, r0
        mov   r2,r0
      c4:	e1a02000 	mov	r2, r0
        mov   fp,r0                     // null frame pointer
      c8:	e1a0b000 	mov	fp, r0
        mov   r7,r0                     // null frame pointer for thumb
      cc:	e1a07000 	mov	r7, r0
        ldr   r10,=main
      d0:	e59fa018 	ldr	sl, [pc, #24]	; f0 <.text+0xf0>
        mov   lr,pc
      d4:	e1a0e00f 	mov	lr, pc
        bx    r10                       // enter main()
      d8:	e12fff1a 	bx	sl

000000dc <_reset>:

        .size   _start, . - _start
        .endfunc

        .global _reset, reset, exit, abort
        .func   _reset
_reset:
reset:
exit:
abort:
#if 0
// Disable interrupts, then force a hardware reset by driving P23 low
// -------------------------------------------------------------------
        mrs   r0,cpsr                   // get PSR
        orr   r0,r0,#I_BIT|F_BIT        // disable IRQ and FIQ
        msr   cpsr,r0                   // set up status register

        ldr   r1,=(PS_BASE)             // PS Base Address
        ldr   r0,=(PS_PIO)              // PIO Module
        str   r0,[r1,#PS_PCER_OFF]      // enable its clock
        ldr   r1,=(PIO_BASE)            // PIO Base Address
        ldr   r0,=(1<<23)               // P23
        str   r0,[r1,#PIO_PER_OFF]      // make sure pin is contolled by PIO
        str   r0,[r1,#PIO_CODR_OFF]     // set the pin low
        str   r0,[r1,#PIO_OER_OFF]      // make it an output
#endif
        b     .                         // loop until reset
      dc:	eafffffe 	b	dc <_reset>
      e0:	00000174 	andeq	r0, r0, r4, ror r1
      e4:	40001124 	andmi	r1, r0, r4, lsr #2
      e8:	40000000 	andmi	r0, r0, r0
      ec:	40000008 	andmi	r0, r0, r8
      f0:	00000180 	andeq	r0, r0, r0, lsl #3

000000f4 <SystemInit>:
{

	// --- enable and connect the PLL (Phase Locked Loop) ---
	// a. set multiplier and divider
	SCB_PLLCFG = MSEL | (1<<PSEL1) | (0<<PSEL0);
      f4:	e59f2074 	ldr	r2, [pc, #116]	; 170 <.text+0x170>
      f8:	e3a03044 	mov	r3, #68	; 0x44
      fc:	e5823084 	str	r3, [r2, #132]
	// b. enable PLL
	SCB_PLLCON = (1<<PLLE);
     100:	e3a03001 	mov	r3, #1	; 0x1
     104:	e5823080 	str	r3, [r2, #128]
	// c. feed sequence
	SCB_PLLFEED = PLL_FEED1;
     108:	e28330a9 	add	r3, r3, #169	; 0xa9
     10c:	e582308c 	str	r3, [r2, #140]
	SCB_PLLFEED = PLL_FEED2;
     110:	e3a03055 	mov	r3, #85	; 0x55
     114:	e582308c 	str	r3, [r2, #140]
	// d. wait for PLL lock (PLOCK bit is set if locked)
	while (!(SCB_PLLSTAT & (1<<PLOCK)));
     118:	e59fc050 	ldr	ip, [pc, #80]	; 170 <.text+0x170>
     11c:	e59c3088 	ldr	r3, [ip, #136]
     120:	e3130b01 	tst	r3, #1024	; 0x400
     124:	0afffffb 	beq	118 <SystemInit+0x24>
	// e. connect (and enable) PLL
	SCB_PLLCON = (1<<PLLE) | (1<<PLLC);
     128:	e3a01003 	mov	r1, #3	; 0x3
	// f. feed sequence
	SCB_PLLFEED = PLL_FEED1;
     12c:	e3a030aa 	mov	r3, #170	; 0xaa
     130:	e58c1080 	str	r1, [ip, #128]
     134:	e58c308c 	str	r3, [ip, #140]
	SCB_PLLFEED = PLL_FEED2;
     138:	e3a03055 	mov	r3, #85	; 0x55
     13c:	e58c308c 	str	r3, [ip, #140]
	
	// --- setup and enable the MAM (Memory Accelerator Module) ---
	// a. start change by turning of the MAM (redundant)
	MAM_MAMCR = 0;	
     140:	e3a03000 	mov	r3, #0	; 0x0
     144:	e58c3000 	str	r3, [ip]
	
	SCB_EXTPOLAR= 0x04;
     148:	e3a02004 	mov	r2, #4	; 0x4
	SCB_EXTINT	= 0x04;
	
	
	// b. set MAM-Fetch cycle to 3 cclk as recommended for >40MHz
	MAM_MAMTIM = MAM_FETCH;
	// c. enable MAM 
	MAM_MAMCR = MAM_MODE;
	
	// --- set VPB speed ---
	SCB_VPBDIV = VPBDIV_VAL;
     14c:	e3a00001 	mov	r0, #1	; 0x1
     150:	e2833002 	add	r3, r3, #2	; 0x2
     154:	e58c214c 	str	r2, [ip, #332]
     158:	e58c2140 	str	r2, [ip, #320]
     15c:	e58c1004 	str	r1, [ip, #4]
     160:	e58c3000 	str	r3, [ip]
     164:	e58c0100 	str	r0, [ip, #256]
	
	// --- map INT-vector ---
	 SCB_MEMMAP = MEMMAP_USER_FLASH_MODE;
     168:	e58c0040 	str	r0, [ip, #64]
}
     16c:	e12fff1e 	bx	lr
     170:	e01fc000 	ands	ip, pc, r0

00000174 <swiirqp>:

void swiirqp (void) 
{	
	printf("\nint\n");
     174:	e59f0000 	ldr	r0, [pc, #0]	; 17c <.text+0x17c>
     178:	ea00031e 	b	df8 <_printf_P>
     17c:	00001970 	andeq	r1, r0, r0, ror r9

00000180 <main>:
}

/*#######################################################################################
Main Programm
#######################################################################################*/
int main(void)