📄 main.lss
字号:
main.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00001d60 00000000 00000000 00008000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 00000008 40000000 40000000 00009d60 2**1
ALLOC
2 .stack 00001024 40000100 40000100 00009d60 2**0
ALLOC
3 .comment 0000010e 00000000 00000000 00009d60 2**0
CONTENTS, READONLY
4 .debug_aranges 00000140 00000000 00000000 00009e70 2**3
CONTENTS, READONLY, DEBUGGING
5 .debug_pubnames 000002b9 00000000 00000000 00009fb0 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_info 000013e8 00000000 00000000 0000a269 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_abbrev 000006da 00000000 00000000 0000b651 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_line 000005f9 00000000 00000000 0000bd2b 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_frame 00000434 00000000 00000000 0000c324 2**2
CONTENTS, READONLY, DEBUGGING
10 .debug_str 00000588 00000000 00000000 0000c758 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_loc 00001141 00000000 00000000 0000cce0 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <_boot>:
// Runtime Interrupt Vectors
// -------------------------
Vectors:
b _start // reset - _start
0: ea000015 b 5c <_mainCRTStartup>
ldr pc,_undf // undefined - _undf
4: e59ff014 ldr pc, [pc, #20] ; 20 <_undf>
ldr pc,_swi // SWI - _swi
8: e59ff014 ldr pc, [pc, #20] ; 24 <_swi>
ldr pc,_pabt // program abort - _pabt
c: e59ff014 ldr pc, [pc, #20] ; 28 <_pabt>
ldr pc,_dabt // data abort - _dabt
10: e59ff014 ldr pc, [pc, #20] ; 2c <_dabt>
nop
14: e1a00000 nop (mov r0,r0)
ldr pc,[pc,#-0xFF0] // IRQ - read the VIC
18: e51ffff0 ldr pc, [pc, #-4080] ; fffff030 <_stack+0xbfffdf0c>
ldr pc,_fiq // FIQ - _fiq
1c: e59ff010 ldr pc, [pc, #16] ; 34 <_fiq>
00000020 <_undf>:
20: 81000004 tsthi r0, r4
00000024 <_swi>:
24: 81000008 tsthi r0, r8
00000028 <_pabt>:
28: 8100000c tsthi r0, ip
0000002c <_dabt>:
2c: 81000010 tsthi r0, r0, lsl r0
00000030 <_irq>:
30: 81000018 tsthi r0, r8, lsl r0
00000034 <_fiq>:
34: 8100001c tsthi r0, ip, lsl r0
00000038 <__undf>:
// Use this group for development
_undf: .word 0x81000004 // undefined
_swi: .word 0x81000008 // SWI
_pabt: .word 0x8100000C // program abort
_dabt: .word 0x81000010 // data abort
_irq: .word 0x81000018 // IRQ
_fiq: .word 0x8100001C // FIQ
__undf: b . // undefined
38: eafffffe b 38 <__undf>
0000003c <__swi>:
__swi: b . // SWI
3c: eafffffe b 3c <__swi>
00000040 <__pabt>:
__pabt: b . // program abort
40: eafffffe b 40 <__pabt>
00000044 <__dabt>:
__dabt: b . // data abort
44: eafffffe b 44 <__dabt>
00000048 <__irq>:
__irq: b . // IRQ
48: eafffffe b 48 <__irq>
0000004c <__fiq>:
__fiq: b . // FIQ
4c: eafffffe b 4c <__fiq>
00000050 <_swiirq>:
.size _boot, . - _boot
.endfunc
// Setup the operating mode & stack.
// ---------------------------------
.global _start, start, _mainCRTStartup
.func _start
_swiirq:
swiirq:
ldr r10,=swiirqp
50: e59fa088 ldr sl, [pc, #136] ; e0 <.text+0xe0>
mov lr,pc
54: e1a0e00f mov lr, pc
bx r10 // enter main()
58: e12fff1a bx sl
0000005c <_mainCRTStartup>:
_start:
start:
_mainCRTStartup:
// Initialize Interrupt System
// - Set stack location for each mode
// - Leave in System Mode with Interrupts Disabled
// -----------------------------------------------
ldr r0,=_stack
5c: e59f0080 ldr r0, [pc, #128] ; e4 <.text+0xe4>
msr CPSR_c,#MODE_UND|I_BIT|F_BIT // Undefined Instruction Mode
60: e321f0db msr CPSR_c, #219 ; 0xdb
mov sp,r0
64: e1a0d000 mov sp, r0
sub r0,r0,#UND_STACK_SIZE
68: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_ABT|I_BIT|F_BIT // Abort Mode
6c: e321f0d7 msr CPSR_c, #215 ; 0xd7
mov sp,r0
70: e1a0d000 mov sp, r0
sub r0,r0,#ABT_STACK_SIZE
74: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_FIQ|I_BIT|F_BIT // FIQ Mode
78: e321f0d1 msr CPSR_c, #209 ; 0xd1
mov sp,r0
7c: e1a0d000 mov sp, r0
sub r0,r0,#FIQ_STACK_SIZE
80: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_IRQ|I_BIT|F_BIT // IRQ Mode
84: e321f0d2 msr CPSR_c, #210 ; 0xd2
mov sp,r0
88: e1a0d000 mov sp, r0
sub r0,r0,#IRQ_STACK_SIZE
8c: e2400080 sub r0, r0, #128 ; 0x80
msr CPSR_c,#MODE_SVC|I_BIT|F_BIT // Supervisor Mode
90: e321f0d3 msr CPSR_c, #211 ; 0xd3
mov sp,r0
94: e1a0d000 mov sp, r0
sub r0,r0,#SVC_STACK_SIZE
98: e2400004 sub r0, r0, #4 ; 0x4
msr CPSR_c,#MODE_SYS|I_BIT|F_BIT // System Mode
9c: e321f0df msr CPSR_c, #223 ; 0xdf
mov sp,r0
a0: e1a0d000 mov sp, r0
// Copy initialized data to its execution address in RAM
// -----------------------------------------------------
#ifdef ROM_RUN
ldr r1,=_etext // -> ROM data start
ldr r2,=_data // -> data start
ldr r3,=_edata // -> end of data
1: cmp r2,r3 // check if data to move
ldrlo r0,[r1],#4 // copy it
strlo r0,[r2],#4
blo 1b // loop until done
#endif
// Clear .bss
// ----------
mov r0,#0 // get a zero
a4: e3a00000 mov r0, #0 ; 0x0
ldr r1,=__bss_start // -> bss start
a8: e59f1038 ldr r1, [pc, #56] ; e8 <.text+0xe8>
ldr r2,=__bss_end__ // -> bss end
ac: e59f2038 ldr r2, [pc, #56] ; ec <.text+0xec>
2: cmp r1,r2 // check if data to clear
b0: e1510002 cmp r1, r2
strlo r0,[r1],#4 // clear 4 bytes
b4: 34810004 strcc r0, [r1], #4
blo 2b // loop until done
b8: 3afffffc bcc b0 <IRQ_STACK_SIZE+0x30>
// Call main program: main(0)
// --------------------------
mov r0,#0 // no arguments (argc = 0)
bc: e3a00000 mov r0, #0 ; 0x0
mov r1,r0
c0: e1a01000 mov r1, r0
mov r2,r0
c4: e1a02000 mov r2, r0
mov fp,r0 // null frame pointer
c8: e1a0b000 mov fp, r0
mov r7,r0 // null frame pointer for thumb
cc: e1a07000 mov r7, r0
ldr r10,=main
d0: e59fa018 ldr sl, [pc, #24] ; f0 <.text+0xf0>
mov lr,pc
d4: e1a0e00f mov lr, pc
bx r10 // enter main()
d8: e12fff1a bx sl
000000dc <_reset>:
.size _start, . - _start
.endfunc
.global _reset, reset, exit, abort
.func _reset
_reset:
reset:
exit:
abort:
#if 0
// Disable interrupts, then force a hardware reset by driving P23 low
// -------------------------------------------------------------------
mrs r0,cpsr // get PSR
orr r0,r0,#I_BIT|F_BIT // disable IRQ and FIQ
msr cpsr,r0 // set up status register
ldr r1,=(PS_BASE) // PS Base Address
ldr r0,=(PS_PIO) // PIO Module
str r0,[r1,#PS_PCER_OFF] // enable its clock
ldr r1,=(PIO_BASE) // PIO Base Address
ldr r0,=(1<<23) // P23
str r0,[r1,#PIO_PER_OFF] // make sure pin is contolled by PIO
str r0,[r1,#PIO_CODR_OFF] // set the pin low
str r0,[r1,#PIO_OER_OFF] // make it an output
#endif
b . // loop until reset
dc: eafffffe b dc <_reset>
e0: 00000178 andeq r0, r0, r8, ror r1
e4: 40001124 andmi r1, r0, r4, lsr #2
e8: 40000000 andmi r0, r0, r0
ec: 40000008 andmi r0, r0, r8
f0: 0000018c andeq r0, r0, ip, lsl #3
000000f4 <SystemInit>:
{
// --- enable and connect the PLL (Phase Locked Loop) ---
// a. set multiplier and divider
SCB_PLLCFG = MSEL | (1<<PSEL1) | (0<<PSEL0);
f4: e3a0220e mov r2, #-536870912 ; 0xe0000000
f8: e282297f add r2, r2, #2080768 ; 0x1fc000
fc: e3a03044 mov r3, #68 ; 0x44
100: e5823084 str r3, [r2, #132]
// b. enable PLL
SCB_PLLCON = (1<<PLLE);
104: e2433043 sub r3, r3, #67 ; 0x43
108: e5823080 str r3, [r2, #128]
// c. feed sequence
SCB_PLLFEED = PLL_FEED1;
10c: e28330a9 add r3, r3, #169 ; 0xa9
110: e582308c str r3, [r2, #140]
SCB_PLLFEED = PLL_FEED2;
114: e2433055 sub r3, r3, #85 ; 0x55
118: e582308c str r3, [r2, #140]
11c: e3a0320e mov r3, #-536870912 ; 0xe0000000
120: e283197f add r1, r3, #2080768 ; 0x1fc000
// d. wait for PLL lock (PLOCK bit is set if locked)
while (!(SCB_PLLSTAT & (1<<PLOCK)));
124: e5913088 ldr r3, [r1, #136]
128: e3130b01 tst r3, #1024 ; 0x400
12c: 0afffffc beq 124 <SystemInit+0x30>
// e. connect (and enable) PLL
SCB_PLLCON = (1<<PLLE) | (1<<PLLC);
130: e3a02003 mov r2, #3 ; 0x3
134: e5812080 str r2, [r1, #128]
// f. feed sequence
SCB_PLLFEED = PLL_FEED1;
138: e3a030aa mov r3, #170 ; 0xaa
13c: e581308c str r3, [r1, #140]
SCB_PLLFEED = PLL_FEED2;
140: e2433055 sub r3, r3, #85 ; 0x55
144: e581308c str r3, [r1, #140]
// --- setup and enable the MAM (Memory Accelerator Module) ---
// a. start change by turning of the MAM (redundant)
MAM_MAMCR = 0;
148: e2433055 sub r3, r3, #85 ; 0x55
14c: e5813000 str r3, [r1]
SCB_EXTPOLAR= 0x04;
150: e2833004 add r3, r3, #4 ; 0x4
154: e581314c str r3, [r1, #332]
SCB_EXTINT = 0x04;
158: e5813140 str r3, [r1, #320]
// b. set MAM-Fetch cycle to 3 cclk as recommended for >40MHz
MAM_MAMTIM = MAM_FETCH;
15c: e5812004 str r2, [r1, #4]
// c. enable MAM
MAM_MAMCR = MAM_MODE;
160: e2433002 sub r3, r3, #2 ; 0x2
164: e5813000 str r3, [r1]
// --- set VPB speed ---
SCB_VPBDIV = VPBDIV_VAL;
168: e2433001 sub r3, r3, #1 ; 0x1
16c: e5813100 str r3, [r1, #256]
// --- map INT-vector ---
SCB_MEMMAP = MEMMAP_USER_FLASH_MODE;
170: e5813040 str r3, [r1, #64]
}
174: e12fff1e bx lr
00000178 <swiirqp>:
void swiirqp (void)
{
178: e52de004 str lr, [sp, #-4]!
printf("\nINT wurde ausgel鰏t\n");
17c: e59f0004 ldr r0, [pc, #4] ; 188 <.text+0x188>
180: eb00036e bl f40 <_printf_P>
}
184: e49df004 ldr pc, [sp], #4
188: 00001bb4 streqh r1, [r0], -r4
0000018c <main>:
/*#######################################################################################
Main Programm
#######################################################################################*/
int main(void)
{
18c: e92d4030 stmdb sp!, {r4, r5, lr}
void (*kernelstart)(void);
SystemInit();
190: ebffffd7 bl f4 <SystemInit>
uart0Init(B9600, UART_8N1, UART_FIFO_OFF); // setup the UART
194: e3a00f61 mov r0, #388 ; 0x184
198: e2800003 add r0, r0, #3 ; 0x3
19c: e3a01003 mov r1, #3 ; 0x3
1a0: e3a02000 mov r2, #0 ; 0x0
1a4: eb0002f5 bl d80 <uart0Init>
PCB_PINSEL2 = 0x0F814924; //Init Extendet Memory
1a8: e3a0253e mov r2, #260046848 ; 0xf800000
1ac: e2822b52 add r2, r2, #83968 ; 0x14800
1b0: e2822f49 add r2, r2, #292 ; 0x124
1b4: e3a0320e mov r3, #-536870912 ; 0xe0000000
1b8: e283390b add r3, r3, #180224 ; 0x2c000
1bc: e5832014 str r2, [r3, #20]
BCFG1 = 0x20000420;
1c0: e3a02eff mov r2, #4080 ; 0xff0
1c4: e282200f add r2, r2, #15 ; 0xf
1c8: e1822a82 orr r2, r2, r2, lsl #21
1cc: e3a03202 mov r3, #536870912 ; 0x20000000
1d0: e2833e42 add r3, r3, #1056 ; 0x420
1d4: e5023ffb str r3, [r2, #-4091]
printf("\n\n\r");
1d8: e59f00e8 ldr r0, [pc, #232] ; 2c8 <.text+0x2c8>
1dc: eb000357 bl f40 <_printf_P>
printf("*******************************************\n\r");
1e0: e59f00e4 ldr r0, [pc, #228] ; 2cc <.text+0x2cc>
1e4: eb000355 bl f40 <_printf_P>
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