📄 uart.lst
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1 .file "uart.c"
9 .Ltext0:
10 .align 2
11 .global uart0Init
13 uart0Init:
14 .LFB2:
15 .file 1 "uart.c"
1:uart.c **** /* *****************************************************************************
2:uart.c **** *
3:uart.c **** * $RCSfile: $
4:uart.c **** * $Revision: $
5:uart.c **** *
6:uart.c **** * This module provides interface routines to the LPC ARM UARTs.
7:uart.c **** * Copyright 2004, R O SoftWare
8:uart.c **** * No guarantees, warrantees, or promises, implied or otherwise.
9:uart.c **** * May be used for hobby or commercial purposes provided copyright
10:uart.c **** * notice remains intact.
11:uart.c **** *
12:uart.c **** * reduced to see what has to be done for minimum UART-support by mthomas
13:uart.c **** *****************************************************************************/
14:uart.c ****
15:uart.c **** // #warning "this is a reduced version of the R O Software code"
16:uart.c ****
17:uart.c **** #include <arch/philips/lpc2119.h>
18:uart.c **** #include "uart.h"
19:uart.c ****
20:uart.c **** /* on LPC210x: UART0 TX-Pin=P0.2, RX-Pin=P0.1
21:uart.c **** PINSEL0 has to be set to "UART-Function" = Function "01"
22:uart.c **** for Pin 0.0 and 0.1 */
23:uart.c ****
24:uart.c **** #define PINSEL_BITPIN0 0
25:uart.c **** #define PINSEL_BITPIN1 2
26:uart.c **** // #define PINSEL_BITPIN2 4
27:uart.c **** #define PINSEL_FIRST_ALT_FUNC 1
28:uart.c **** // #define PINSEL_SECOND_ALT_FUNC 2
29:uart.c ****
30:uart.c **** // Values of Bits 0-3 in PINSEL to activate UART0
31:uart.c **** #define UART0_PINSEL ((PINSEL_FIRST_ALT_FUNC<<PINSEL_BITPIN0)|(PINSEL_FIRST_ALT_FUNC<<PINSEL_BIT
32:uart.c **** // Mask of Bits 0-4
33:uart.c **** #define UART0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */
34:uart.c ****
35:uart.c **** // U0_LCR devisor latch bit
36:uart.c **** #define UART0_LCR_DLAB 7
37:uart.c ****
38:uart.c **** /* baudrate divisor - use UART_BAUD macro
39:uart.c **** * mode - see typical modes (uart.h)
40:uart.c **** * fmode - see typical fmodes (uart.h)
41:uart.c **** * NOTE: uart0Init(UART_BAUD(9600), UART_8N1, UART_FIFO_8);
42:uart.c **** */
43:uart.c **** void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)
44:uart.c **** {
16 args = 0, pretend = 0, frame = 0
17 @ frame_needed = 0, uses_anonymous_args = 0
18 .LVL0:
19 str lr, [sp, #-4]!
20 0000 04E02DE5 .LCFI0:
21 and r2, r2, #255
22 0004 FF2002E2 .loc 1 48 0
45:uart.c **** // setup Pin Function Select Register (Pin Connect Block)
46:uart.c **** // make sure old values of Bits 0-4 are masked out and
47:uart.c **** // set them according to UART0-Pin-Selection
48:uart.c **** PCB_PINSEL0 = (PCB_PINSEL0 & ~UART0_PINMASK) | UART0_PINSEL;
23 , #-536870912
24 0008 0EC2A0E3 add lr, ip, #180224
25 000c 0BE98CE2 ldr r3, [lr, #0]
26 0010 00309EE5 bic r3, r3, #15
27 0014 0F30C3E3 orr r3, r3, #5
28 0018 053083E3 str r3, [lr, #0]
29 001c 00308EE5 .loc 1 50 0
49:uart.c ****
50:uart.c **** UART0_IER = 0x00; // disable all interrupts
30 , ip, #49152
31 0020 03C98CE2 mov r3, #0
32 0024 0030A0E3 str r3, [ip, #4]
33 0028 04308CE5 .loc 1 51 0
51:uart.c **** UART0_IIR = 0x00; // clear interrupt ID register
34 r3, [ip, #8]
35 002c 08308CE5 .loc 1 52 0
52:uart.c **** UART0_LSR = 0x00; // clear line status register
36 tr r3, [ip, #20]
37 0030 14308CE5 .loc 1 55 0
53:uart.c ****
54:uart.c **** // set the baudrate - DLAB must be set to access DLL/DLM
55:uart.c **** UART0_LCR = (1<<UART0_LCR_DLAB); // set divisor latches (DLAB)
38 dd r3, r3, #128
39 0034 803083E2 str r3, [ip, #12]
40 0038 0C308CE5 .loc 1 56 0
56:uart.c **** UART0_DLL = (uint8_t)baud; // set for baud low byte
41 d r3, r0, #255
42 003c FF3000E2 str r3, [ip, #0]
43 0040 00308CE5 .loc 1 57 0
57:uart.c **** UART0_DLM = (uint8_t)(baud >> 8); // set for baud high byte
44 v r0, r0, lsr #8
45 0044 2004A0E1 .LVL1:
46 and r0, r0, #255
47 0048 FF0000E2 str r0, [ip, #4]
48 004c 04008CE5 .loc 1 62 0
58:uart.c ****
59:uart.c **** // set the number of characters and other
60:uart.c **** // user specified operating parameters
61:uart.c **** // Databits, Parity, Stopbits - Settings in Line Control Register
62:uart.c **** UART0_LCR = (mode & ~(1<<UART0_LCR_DLAB)); // clear DLAB "on-the-fly"
49 r1, r1, #127
50 0050 7F1001E2 .LVL2:
51 str r1, [ip, #12]
52 0054 0C108CE5 .loc 1 64 0
63:uart.c **** // setup FIFO Control Register (fifo-enabled + xx trig)
64:uart.c **** UART0_FCR = fmode;
53 r2, [ip, #8]
54 0058 08208CE5 .loc 1 65 0
65:uart.c **** }
55 dr pc, [sp], #4
56 005c 04F09DE4 .LFE2:
58 .align 2
59 .global uart0Putch
61 uart0Putch:
62 .LFB4:
63 .loc 1 73 0
66:uart.c ****
67:uart.c **** void uart_sendchar(char c)
68:uart.c **** {
69:uart.c **** uart0Putch(c);
70:uart.c **** }
71:uart.c ****
72:uart.c **** int uart0Putch(int ch)
73:uart.c **** {
64 0, pretend = 0, frame = 0
65 @ frame_needed = 0, uses_anonymous_args = 0
66 @ link register save eliminated.
67 .LVL3:
68 @ lr needed for prologue
69 mov r3, #-536870912
70 0060 0E32A0E3 add r2, r3, #49152
71 0064 032983E2 .L5:
72 .loc 1 74 0
74:uart.c **** while (!(UART0_LSR & ULSR_THRE)) // wait for TX buffer to empty
73 [r2, #20]
74 0068 143092E5 tst r3, #32
75 006c 200013E3 beq .L5
76 0070 FCFFFF0A .loc 1 77 0
75:uart.c **** continue; // also either WDOG() or swap()
76:uart.c ****
77:uart.c **** UART0_THR = (uint8_t)ch; // put char to Transmit Holding Register
77 r0, r0, #255
78 0074 FF0000E2 .LVL4:
79 str r0, [r2, #0]
80 0078 000082E5 .loc 1 79 0
78:uart.c **** return (uint8_t)ch; // return char ("stdio-compatible"?)
79:uart.c **** }
81 lr
82 007c 1EFF2FE1 .LFE4:
84 .align 2
85 .global uart_sendchar
87 uart_sendchar:
88 .LFB3:
89 .loc 1 68 0
90 @ args = 0, pretend = 0, frame = 0
91 @ frame_needed = 0, uses_anonymous_args = 0
92 .LVL5:
93 str lr, [sp, #-4]!
94 0080 04E02DE5 .LCFI1:
95 and r0, r0, #255
96 0084 FF0000E2 .loc 1 69 0
97 bl uart0Putch
98 0088 FEFFFFEB .LVL6:
99 .loc 1 70 0
100 ldr pc, [sp], #4
101 008c 04F09DE4 .LFE3:
103 .align 2
104 .global uart0Puts
106 uart0Puts:
107 .LFB5:
108 .loc 1 82 0
80:uart.c ****
81:uart.c **** const char *uart0Puts(const char *string)
82:uart.c **** {
109 ame = 0
110 @ frame_needed = 0, uses_anonymous_args = 0
111 .LVL7:
112 stmfd sp!, {r4, lr}
113 0090 10402DE9 .LCFI2:
114 mov r4, r0
115 0094 0040A0E1 .loc 1 85 0
83:uart.c **** char ch;
84:uart.c ****
85:uart.c **** while ((ch = *string)) {
116 0, [r0, #0] @ zero_extendqisi2
117 0098 0000D0E5 .LVL8:
118 cmp r0, #0
119 009c 000050E3 beq .L13
120 00a0 0500000A .L17:
121 .loc 1 86 0
86:uart.c **** if (uart0Putch(ch)<0) break;
122 rt0Putch
123 00a4 FEFFFFEB .LVL9:
124 cmp r0, #0
125 00a8 000050E3 blt .L13
126 00ac 020000BA .loc 1 85 0
127 ldrb r0, [r4, #1]! @ zero_extendqisi2
128 00b0 0100F4E5 .LVL10:
129 cmp r0, #0
130 00b4 000050E3 bne .L17
131 00b8 F9FFFF1A .L13:
132 .loc 1 91 0
87:uart.c **** string++;
88:uart.c **** }
89:uart.c ****
90:uart.c **** return string;
91:uart.c **** }
133
134 00bc 0400A0E1 .LVL11:
135 ldmfd sp!, {r4, pc}
136 00c0 1080BDE8 .LFE5:
138 .align 2
139 .global uart0TxEmpty
141 uart0TxEmpty:
142 .LFB6:
143 .loc 1 94 0
92:uart.c ****
93:uart.c **** int uart0TxEmpty(void)
94:uart.c **** {
144 0, pretend = 0, frame = 0
145 @ frame_needed = 0, uses_anonymous_args = 0
146 @ link register save eliminated.
147 @ lr needed for prologue
148 .loc 1 95 0
95:uart.c **** return (UART0_LSR & (ULSR_THRE | ULSR_TEMT)) == (ULSR_THRE | ULSR_TEMT);
149 r3, #-536870912
150 00c4 0E32A0E3 add r3, r3, #49152
151 00c8 033983E2 ldr r0, [r3, #20]
152 00cc 140093E5 and r0, r0, #96
153 00d0 600000E2 .loc 1 96 0
96:uart.c **** }
154 r0, #96
155 00d4 600050E3 movne r0, #0
156 00d8 0000A013 moveq r0, #1
157 00dc 0100A003 bx lr
158 00e0 1EFF2FE1 .LFE6:
160 .align 2
161 .global uart0TxFlush
163 uart0TxFlush:
164 .LFB7:
165 .loc 1 99 0
97:uart.c ****
98:uart.c **** void uart0TxFlush(void)
99:uart.c **** {
166 pretend = 0, frame = 0
167 @ frame_needed = 0, uses_anonymous_args = 0
168 @ link register save eliminated.
169 @ lr needed for prologue
170 .loc 1 100 0
100:uart.c **** UART0_FCR |= UFCR_TX_FIFO_RESET; // clear the TX fifo
171 r2, #-536870912
172 00e4 0E22A0E3 add r2, r2, #49152
173 00e8 032982E2 ldr r3, [r2, #8]
174 00ec 083092E5 orr r3, r3, #4
175 00f0 043083E3 str r3, [r2, #8]
176 00f4 083082E5 .loc 1 101 0
101:uart.c **** }
177
178 00f8 1EFF2FE1 .LFE7:
180 .align 2
181 .global uart0Getch
183 uart0Getch:
184 .LFB8:
185 .loc 1 106 0
102:uart.c ****
103:uart.c ****
104:uart.c **** /* Returns: character on success, -1 if no character is available */
105:uart.c **** int uart0Getch(void)
106:uart.c **** {
186 = 0, pretend = 0, frame = 0
187 @ frame_needed = 0, uses_anonymous_args = 0
188 @ link register save eliminated.
189 @ lr needed for prologue
190 .loc 1 107 0
107:uart.c **** if (UART0_LSR & ULSR_RDR) // check if character is available
191 r3, #-536870912
192 00fc 0E32A0E3 add r3, r3, #49152
193 0100 033983E2 ldr r3, [r3, #20]
194 0104 143093E5 tst r3, #1
195 0108 010013E3 mvneq r0, #0
196 010c 0000E003 .loc 1 108 0
108:uart.c **** return UART0_RBR; // return character
197 r3, #-536870912
198 0110 0E32A013 addne r3, r3, #49152
199 0114 03398312 ldrne r0, [r3, #0]
200 0118 00009315 .loc 1 111 0
109:uart.c ****
110:uart.c **** return -1;
111:uart.c **** }
201 lr
202 011c 1EFF2FE1 .LFE8:
204 .section .debug_frame,"",%progbits
298 .section .debug_loc,"",%progbits
DEFINED SYMBOLS
*ABS*:00000000 uart.c
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:13 .text:00000000 uart0Init
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:20 .text:00000000 $a
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:62 .text:00000060 uart0Putch
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:88 .text:00000080 uart_sendchar
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:107 .text:00000090 uart0Puts
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:142 .text:000000c4 uart0TxEmpty
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:164 .text:000000e4 uart0TxFlush
C:\DOKUME~1\root\LOKALE~1\Temp/ccq0aaaa.s:184 .text:000000fc uart0Getch
NO UNDEFINED SYMBOLS
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