📄 cy4623_rdk.lst
字号:
0125: 15 00 SUB [X+0],A
0127: 16 00 3D SUB [is_ps2],61
012A: 1F 2B 00 SBB [X+43],0
012D: 31 82 XOR A,130
012F: 2A 00 OR A,[0]
0131: 73 CPL A
0132: 00 SWI
0133: FF E0 INDEX 0x0115
0135: 01 E3 ADD A,227
0137: 14 FF SUB [255],A
0139: 01 00 ADD A,0
013B: 00 SWI
013C: 00 SWI
013D: 01 01 ADD A,1
013F: 42 01 8B AND REG[X+1],139
0142: 01 01 ADD A,1
0144: 4D 01 SWAP X,[shouldSuspend]
0146: 47 01 4F TST [is_ps2+1],79
0149: 01 5A ADD A,90
014B: 01 51 ADD A,81
014D: 80 7F JMP 0x01CD
014F: 01 63 ADD A,99
0151: 00 SWI
0152: 00 SWI
0153: 00 SWI
0154: 09 07 ADC A,7
0156: 14 00 SUB [is_ps2],A
0158: 00 SWI
0159: DE 00 JNC 0xFF5A
015B: 00 SWI
015C: 00 SWI
015D: 34 07 XOR [7],A
015F: 24 00 AND [is_ps2],A
0161: 00 SWI
0162: DE 04 JNC 0xFF67
0164: 01 70 ADD A,112
0166: 00 SWI
0167: 00 SWI
0168: 01 79 ADD A,121
016A: 00 SWI
016B: 00 SWI
016C: 01 82 ADD A,130
016E: 00 SWI
016F: 00 SWI
0170: 00 SWI
0171: 01 00 ADD A,0
0173: 08 PUSH A
0174: 00 SWI
0175: 41 00 00 AND REG[0],0
0178: DE 00 JNC 0xFF79
017A: 01 00 ADD A,0
017C: 00 SWI
017D: 00 SWI
017E: 49 00 00 TST REG[0],0
0181: DE 00 JNC 0xFF82
0183: 01 00 ADD A,0
0185: 00 SWI
0186: 00 SWI
0187: 51 00 MOV A,[is_ps2]
0189: 00 SWI
018A: DE 00 JNC 0xFF8B
018C: 00 SWI
018D: 00 SWI
018E: 22 07 AND A,[7]
0190: 02 00 ADD A,[is_ps2]
0192: 00 SWI
0193: DE 00 JNC 0xFF94
0195: 00 SWI
0196: 00 SWI
0197: 12 06 SUB A,[__r0]
0199: F0 00 INDEX 0x019B
019B: 00 SWI
019C: DE 55 JNC 0xFFF2
FILE: lib\psocconfig.asm
(0001) ; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
(0002) ;
(0003) ;==========================================================================
(0004) ; PSoCConfig.asm
(0005) ; @PSOC_VERSION
(0006) ;
(0007) ; Version: 0.85
(0008) ; Revised: June 22, 2004
(0009) ; Copyright Cypress MicroSystems 2000-2004. All Rights Reserved.
(0010) ;
(0011) ; This file is generated by the Device Editor on Application Generation.
(0012) ; It contains code which loads the configuration data table generated in
(0013) ; the file PSoCConfigTBL.asm
(0014) ;
(0015) ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
(0016) ; Edits to this file will not be preserved.
(0017) ;==========================================================================
(0018) ;
(0019) include "m8c.inc"
(0020) include "memory.inc"
(0021) include "GlobalParams.inc"
(0022)
(0023) export LoadConfigInit
(0024) export _LoadConfigInit
(0025) export LoadConfig_cy4623_rdk
(0026) export _LoadConfig_cy4623_rdk
(0027) export Port_1_Data_SHADE
(0028) export _Port_1_Data_SHADE
(0029)
(0030)
(0031) export NO_SHADOW
(0032) export _NO_SHADOW
(0033)
(0034) FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
(0035) END_CONFIG_TABLE: equ ffh ;end of config table indicator
(0036)
(0037) AREA psoc_config(rom, rel)
(0038)
(0039) ;---------------------------------------------------------------------------
(0040) ; LoadConfigInit - Establish the start-up configuration (except for a few
(0041) ; parameters handled by boot code, like CPU speed). This
(0042) ; function can be called from user code, but typically it
(0043) ; is only called from boot.
(0044) ;
(0045) ; INPUTS: None.
(0046) ; RETURNS: Nothing.
(0047) ; SIDE EFFECTS: Registers are volatile: the A and X registers can be modified!
(0048) ; In the large memory model currently only the page
(0049) ; pointer registers listed below are modified. This does
(0050) ; not guarantee that in future implementations of this
(0051) ; function other page pointer registers will not be
(0052) ; modified.
(0053) ;
(0054) ; Page Pointer Registers Modified:
(0055) ; CUR_PP
(0056) ;
(0057) _LoadConfigInit:
(0058) LoadConfigInit:
(0059) RAM_PROLOGUE RAM_USE_CLASS_4
(0060)
019E: 07 00 7C ADD [X+0],124 (0061) mov [Port_1_Data_SHADE], 0h
(0062)
01A1: 01 00 ADD A,0 (0063) lcall LoadConfigTBL_cy4623_rdk_Ordered
01A3: 7C 01 A7 LCALL 0x01A7 (0064) lcall LoadConfig_cy4623_rdk
(0065)
(0066) RAM_EPILOGUE RAM_USE_CLASS_4
01A6: 7F RET (0067) ret
(0068)
(0069) ;---------------------------------------------------------------------------
(0070) ; Load Configuration cy4623_rdk
(0071) ;
(0072) ; Load configuration registers for cy4623_rdk.
(0073) ; IO Bank 0 registers a loaded first,then those in IO Bank 1.
(0074) ;
(0075) ; INPUTS: None.
(0076) ; RETURNS: Nothing.
(0077) ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
(0078) ; modified as may the Page Pointer registers!
(0079) ; In the large memory model currently only the page
(0080) ; pointer registers listed below are modified. This does
(0081) ; not guarantee that in future implementations of this
(0082) ; function other page pointer registers will not be
(0083) ; modified.
(0084) ;
(0085) ; Page Pointer Registers Modified:
(0086) ; CUR_PP
(0087) ;
(0088) _LoadConfig_cy4623_rdk:
(0089) LoadConfig_cy4623_rdk:
(0090) RAM_PROLOGUE RAM_USE_CLASS_4
(0091)
01A7: 10 PUSH X (0092) push x
01A8: 70 EF AND F,239 (0093) M8C_SetBank0 ; Force bank 0
01AA: 50 00 MOV A,0 (0094) mov a, 0 ; Specify bank 0
01AC: 67 ASR A (0095) asr a ; Store in carry flag
(0096) ; Load bank 0 table:
01AD: 50 01 MOV A,1 (0097) mov A, >LoadConfigTBL_cy4623_rdk_Bank0
01AF: 57 01 MOV X,1 (0098) mov X, <LoadConfigTBL_cy4623_rdk_Bank0
01B1: 7C 01 C0 LCALL 0x01C0 (0099) lcall LoadConfig ; Load the bank 0 values
(0100)
01B4: 50 01 MOV A,1 (0101) mov a, 1 ; Specify bank 1
01B6: 67 ASR A (0102) asr a ; Store in carry flag
(0103) ; Load bank 1 table:
01B7: 50 01 MOV A,1 (0104) mov A, >LoadConfigTBL_cy4623_rdk_Bank1
01B9: 57 34 MOV X,52 (0105) mov X, <LoadConfigTBL_cy4623_rdk_Bank1
01BB: 7C 01 C0 LCALL 0x01C0 (0106) lcall LoadConfig ; Load the bank 1 values
(0107)
01BE: 20 POP X (0108) pop x
(0109)
(0110) RAM_EPILOGUE RAM_USE_CLASS_4
01BF: 7F RET (0111) ret
(0112)
(0113)
(0114)
(0115)
(0116) ;---------------------------------------------------------------------------
(0117) ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
(0118) ; pairs. Terminate on address=0xFF.
(0119) ;
(0120) ; INPUTS: [A,X] points to the table to be loaded
(0121) ; Flag Register Carry bit encodes the Register Bank
(0122) ; (Carry=0 => Bank 0; Carry=1 => Bank 1)
(0123) ;
(0124) ; RETURNS: nothing.
(0125) ;
(0126) ; STACK FRAME: X-4 I/O Bank 0/1 indicator
(0127) ; X-3 Temporary store for register address
(0128) ; X-2 LSB of config table address
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